Re: [edk2] SF.net SVN: edk2:[15076] trunk/edk2/MdePkg/Include/IndustryStandard

Subject: Re: [edk2] SF.net SVN: edk2:[15076] trunk/edk2/MdePkg/Include/IndustryStandard

From: "Carsey, Jaben" <jaben.carsey@intel.com>

To: "edk2-devel@lists.sourceforge.net" <edk2-devel@lists.sourceforge.net>

Date: 2014-01-10 05:57:19

  • 2014-01-10 05:57:19  "Carsey, Jaben"   Re: [edk2] SF.net SVN: edk2:[15076] trunk/edk2/MdePkg/Include/IndustryStandard
Please note that I made my commits in the incorrect order today.  This commit is required for the shell commit I made this morning to build/function.

-Jaben

-----Original Message-----
From: jcarsey@users.sourceforge.net [mailto:jcarsey@users.sourceforge.net] 
Sent: Thursday, January 09, 2014 1:55 PM
To: edk2-commits@lists.sourceforge.net
Subject: SF.net SVN: edk2:[15076] trunk/edk2/MdePkg/Include/IndustryStandard

Revision: 15076
          http://sourceforge.net/p/edk2/code/15076
Author:   jcarsey
Date:     2014-01-09 21:55:03 +0000 (Thu, 09 Jan 2014)
Log Message:
-----------
MdePkg: Add PCI Express 2.1 and 3.0 structures

This adds PCI Express extended capabilities structures.  These structures are required for enhancements to the shell.

Contributed-under: TianoCore Contribution Agreement 1.0
Signed-off-by: Jaben Carsey 
Reviewed-by: Ruiyu Ni 

Modified Paths:
--------------
    trunk/edk2/MdePkg/Include/IndustryStandard/Pci.h
    trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress21.h

Added Paths:
-----------
    trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress30.h

Modified: trunk/edk2/MdePkg/Include/IndustryStandard/Pci.h
===================================================================
--- trunk/edk2/MdePkg/Include/IndustryStandard/Pci.h	2014-01-09 19:15:06 UTC (rev 15075)
+++ trunk/edk2/MdePkg/Include/IndustryStandard/Pci.h	2014-01-09 21:55:03 UTC (rev 15076)
@@ -1,7 +1,7 @@
 /** @file
   Support for the latest PCI standard.
 
-Copyright (c) 2006 - 2013, Intel Corporation. All rights reserved.
+Copyright (c) 2006 - 2014, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License that accompanies this distribution. The full text of the license may be found at @@ -17,6 +17,7 @@ #include #include +#include #include #endif Modified: trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress21.h =================================================================== --- trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress21.h 2014-01-09 19:15:06 UTC (rev 15075) +++ trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress21.h 2014-01-09 21:55:03 UTC (rev 15076) @@ -1,7 +1,7 @@ /** @file Support for the latest PCI standard. - Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.
+ Copyright (c) 2006 - 2014, Intel Corporation. All rights + reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at @@ -70,4 +70,218 @@ #define EFI_PCIE_CAPABILITY_ID_SRIOV_BAR5 0x38 #define EFI_PCIE_CAPABILITY_ID_SRIOV_VF_MIGRATION_STATE 0x3C +typedef struct { + UINT32 CapabilityId:16; + UINT32 CapabilityVersion:4; + UINT32 NextCapabilityOffset:12; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER; + +#define PCI_EXP_EXT_HDR PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_ID 0x0001 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER1 +0x1 #define +PCI_EXPRESS_EXTENDED_CAPABILITY_ADVANCED_ERROR_REPORTING_VER2 0x2 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 UncorrectableErrorStatus; + UINT32 UncorrectableErrorMask; + UINT32 UncorrectableErrorSeverity; + UINT32 CorrectableErrorStatus; + UINT32 CorrectableErrorMask; + UINT32 AdvancedErrorCapabilitiesAndControl; + UINT32 HeaderLog; + UINT32 RootErrorCommand; + UINT32 RootErrorStatus; + UINT16 ErrorSourceIdentification; + UINT16 CorrectableErrorSourceIdentification; + UINT32 TlpPrefixLog[4]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_ADVANCED_ERROR_REPORTING; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_ID 0x0002 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_MFVC 0x0009 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VIRTUAL_CHANNEL_VER1 0x1 + +typedef struct { + UINT32 VcResourceCapability:24; + UINT32 PortArbTableOffset:8; + UINT32 VcResourceControl; + UINT16 Reserved1; + UINT16 VcResourceStatus; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 ExtendedVcCount:3; + UINT32 PortVcCapability1:29; + UINT32 PortVcCapability2:24; + UINT32 VcArbTableOffset:8; + UINT16 PortVcControl; + UINT16 PortVcStatus; + PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_VC Capability[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_ID 0x0003 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SERIAL_NUMBER_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT64 SerialNumber; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_SERIAL_NUMBER; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_ID 0x0005 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 ElementSelfDescription; + UINT32 Reserved; + UINT32 LinkEntry[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_LINK_DECLARATION; + +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_DECLARATION_GET_LINK_COUNT(LINK_DE +CLARATION) +(UINT8)(((LINK_DECLARATION->ElementSelfDescription)&0x0000ff00)>>8) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_ID 0x0006 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LINK_CONTROL_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 RootComplexLinkCapabilities; + UINT16 RootComplexLinkControl; + UINT16 RootComplexLinkStatus; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_INTERNAL_LINK_CONTROL; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_ID 0x0004 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_POWER_BUDGETING_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 DataSelect:8; + UINT32 Reserved:24; + UINT32 Data; + UINT32 PowerBudgetCapability:1; + UINT32 Reserved2:7; + UINT32 Reserved3:24; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_POWER_BUDGETING; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_ID 0x000D +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 AcsCapability; + UINT16 AcsControl; + UINT8 EgressControlVectorArray[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_ACS_EXTENDED; + +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_CONTROL(ACS_EXTE +NDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x00000020)) +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_ACS_EXTENDED_GET_EGRES_VECTOR_SIZE(ACS_ +EXTENDED) (UINT8)(((ACS_EXTENDED->AcsCapability)&0x0000FF00)) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_ID 0x0007 +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION_VE +R1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 AssociationBitmap; +} +PCI_EXPRESS_EXTENDED_CAPABILITIES_EVENT_COLLECTOR_ENDPOINT_ASSOCIATION; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_ID 0x0008 +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_MULTI_FUNCTION_VIRTUAL_CHANNEL_VER1 +0x1 + +typedef PCI_EXPRESS_EXTENDED_CAPABILITIES_VIRTUAL_CHANNEL_CAPABILITY +PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTI_FUNCTION_VIRTUAL_CHANNEL_CAPABI +LITY; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_ID 0x000B +#define PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 VendorSpecificHeader; + UINT8 VendorSpecific[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_VENDOR_SPECIFIC; + +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_VENDOR_SPECIFIC_GET_SIZE(VENDOR) +(UINT16)(((VENDOR->VendorSpecificHeader)&0xFFF00000)>>20) + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_ID 0x000A +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RCRB_HEADER_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 VendorId; + UINT16 DeviceId; + UINT32 RcrbCapabilities; + UINT32 RcrbControl; + UINT32 Reserved; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RCRB_HEADER; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_ID 0x0012 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_MULTICAST_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 MultiCastCapability; + UINT16 MulticastControl; + UINT64 McBaseAddress; + UINT64 McReceiveAddress; + UINT64 McBlockAll; + UINT64 McBlockUntranslated; + UINT64 McOverlayBar; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_MULTICAST; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_ID 0x0015 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_RESIZABLE_BAR_VER1 0x1 + +typedef struct { + UINT32 ResizableBarCapability; + UINT16 ResizableBarControl; + UINT16 Reserved; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY; + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR_ENTRY Capability[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_RESIZABLE_BAR; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_ID 0x000E +#define PCI_EXPRESS_EXTENDED_CAPABILITY_ARI_CAPABILITY_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 AriCapability; + UINT16 AriControl; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_ARI_CAPABILITY; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_ID 0x0016 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_VER1 +0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 DpaCapability; + UINT32 DpaLatencyIndicator; + UINT16 DpaStatus; + UINT16 DpaControl; + UINT8 DpaPowerAllocationArray[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_DYNAMIC_POWER_ALLOCATION; + +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_DYNAMIC_POWER_ALLOCATION_GET_SUBSTATE_M +AX(POWER) (UINT16)(((POWER->DpaCapability)&0x0000000F)) + + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_ID 0x0018 +#define +PCI_EXPRESS_EXTENDED_CAPABILITY_LATENCE_TOLERANCE_REPORTING_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT16 MaxSnoopLatency; + UINT16 MaxNoSnoopLatency; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_LATENCE_TOLERANCE_REPORTING; + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_ID 0x0017 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_TPH_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 TphRequesterCapability; + UINT32 TphRequesterControl; + UINT16 TphStTable[1]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_TPH; + #endif Added: trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress30.h =================================================================== --- trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress30.h (rev 0) +++ trunk/edk2/MdePkg/Include/IndustryStandard/PciExpress30.h 2014-01-09 21:55:03 UTC (rev 15076) @@ -0,0 +1,32 @@ +/** @file + Support for the PCI Express 3.0 standard. + + This header file may not define all structures. Please extend as required. + + Copyright (c) 2014, Intel Corporation. All rights reserved.
+ This program and the accompanying materials + are licensed and made available under the terms and conditions of the BSD License + which accompanies this distribution. The full text of the license may be found at + http://opensource.org/licenses/bsd-license.php + + THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, + WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED. + +**/ + +#ifndef _PCIEXPRESS30_H_ +#define _PCIEXPRESS30_H_ + +#include "PciExpress21.h" + +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_ID 0x0019 +#define PCI_EXPRESS_EXTENDED_CAPABILITY_SECONDARY_PCIE_VER1 0x1 + +typedef struct { + PCI_EXPRESS_EXTENDED_CAPABILITIES_HEADER Header; + UINT32 LinkControl3; + UINT32 LaneErrorStatus; + UINT16 EqualizationControl[2]; +} PCI_EXPRESS_EXTENDED_CAPABILITIES_SECONDARY_PCIE; + +#endif This was sent by the SourceForge.net collaborative development platform, the world's largest Open Source development site. ------------------------------------------------------------------------------ CenturyLink Cloud: The Leader in Enterprise Cloud Services. Learn Why More Businesses Are Choosing CenturyLink Cloud For Critical Workloads, Development Environments & Everything In Between. Get a Quote or Start a Free Trial Today. http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk _______________________________________________ edk2-commits mailing list edk2-commits@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-commits ------------------------------------------------------------------------------ CenturyLink Cloud: The Leader in Enterprise Cloud Services. Learn Why More Businesses Are Choosing CenturyLink Cloud For Critical Workloads, Development Environments & Everything In Between. Get a Quote or Start a Free Trial Today. http://pubads.g.doubleclick.net/gampad/clk?id=119420431&iu=/4140/ostg.clktrk _______________________________________________ edk2-devel mailing list edk2-devel@lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/edk2-devel