[edk2]答复: switch to 64 bit mode at PEI phase in X86

Subject: [edk2]答复: switch to 64 bit mode at PEI phase in X86

From: "stanley.ganyezu" <stanley.ganyezu@gmail.com>

To: "'Andrew Fish'" <afish@apple.com>, "'Brian J. Johnson'" <bjohnson@sgi.com>

Date: 2013-07-23 16:38:15

Thanks for Andrew and Brian. Do somebody ever succeed before?

----------
: Andrew Fish [mailto:afish@apple.com] 
: 2013723 7:36
: Brian J. Johnson
: stanley.ganyezu; edk2-devel@lists.sourceforge.net
: Re: [edk2] switch to 64 bit mode at PEI phase in X86

Most of the X64 (x86_64) processors I know about crash and die hard if you
place page tables in the Cache as RAM or the FLASH. That is why you see IA32
PEI and X64 DXE on this class of systems. 

It is possible to use PAE in IA32 mode to access memory above 4 GB,
http://en.wikipedia.org/wiki/Physical_Address_Extension

Thanks,

Andrew Fish


On Jul 22, 2013, at 3:16 PM, "Brian J. Johnson"  wrote:

> On 07/22/2013 08:55 AM, stanley.ganyezu wrote:
>> Hi Everyone,
>> 
>>          I want to access address above 4Gb at PEI phase in X86. Can we
>> switch to 64 bit mode before MRC?
> 
> I wouldn't call myself a real expert on X86 addressing modes, but here 
> are some thoughts:
> 
> AFAIK the PEI core and common modules work just fine in 64-bit mode.  So 
> that's good.
> 
> If you don't have RAM available, i.e. if you're running on real hardware 
> as opposed to a virtual machine or emulator, switching to 64-bit mode 
> may be difficult.  Running C code before RAM is initialized requires 
> putting the CPU in cache-as-RAM mode, where it uses the CPU caches as a 
> small amount of RAM.  I'm not sure if it's possible to use cache-as-RAM 
> in 64-bit mode... you'd need to read the CPU manufacturer's docs pretty 
> carefully to find out.  (I've never seen it done, but that doesn't 
> necessarily mean it's impossible... SMM was never run in 64-bit mode in 
> the past, and I was told it was impossible, but now it's done regularly.)
> 
> A big "gotcha" for 64-bit mode is that it requires writable page tables, 
> which requires generating the required tables in your cache-as-RAM in 
> 32-bit mode (which uses several 4k pages of space, unless you're really 
> clever about repurposing the unused table entries for other data) or 
> implementing a TLB miss handler.  If you can map all addresses with 
> gigabyte-sized pages, and especially if you don't need to access the 
> entire address space before MRC, the tables shouldn't take that much 
> space.  If you try to map a 2^46 address space with 4k pages, your 
> tables will never fit in cache-as-RAM....
> 
> You may need to switch back to 32-bit mode to exit cache-as-RAM... not 
> sure just what that dance would look like.  It would probably take some 
> experimentation.
> 
> There may be other issues I haven't thought of.  Good luck!
> -- 
> 
>                                                 Brian J. Johnson
> 
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