Re: [edk2] [SeaBIOS] (PAM stuff) reset doesn't work on OVMF + SeaBIOS CSM

Subject: Re: [edk2] [SeaBIOS] (PAM stuff) reset doesn't work on OVMF + SeaBIOS CSM

From: Andrew Fish <afish@apple.com>

To: edk2-devel@lists.sourceforge.net

Date: 2013-02-14 22:58:34


On Feb 14, 2013, at 2:09 PM, "H. Peter Anvin"  wrote:

> On 02/14/2013 01:27 PM, David Woodhouse wrote:
>> 
>> So it *is* jumping to 0xfffffff0 but the memory at that location isn't
>> what we expect? Do the PAM registers affect *that* too, or only the
>> region from 0xc0000-0xfffff? Surely the contents at 4GiB- should be
>> unchanged by *anything* we do with the PAM registers?
>> 
>> Or maybe not... after also downloading the i440fx data sheet, I'm even
>> more confused. There's some aliasing with... not the region at 1MiB-
>> but the region at 16MiB-:
>> 

I don't remember the specific registers for the 440BX....

 The i486 moved the reset vector to 0xFFFFFFF0, but it is in real mode. The processor CS register has some magic internal value that lets you run real mode code  up high, but the 1st long jmp you do sends you down low. Thus the chipset needs to alias 0xF000:0xFFF0 to the high address. If you BIOS is written in protected mode then it will turn on the HIgh BIOS Area and jump back into the just under the 4GB region and now it has access to a ROM that can be up to 2MB in size after it turns on the high BIOS area. 

If you hardware reset the PAM registers should get set back to defaults, and CPU goes into the reset state.
If you soft (also called warm) reset, jump to 0xF000:0xFFF0 then, you are not running the reset code in ROM (called SEC in the PI lingo) you are running the shadowed copy from memory provided by the SeaBIOS for  compatibility. 

Thanks,

Andrew

>> (From 4.1 System Address Map):
>> 
>> 2. High BIOS Area (FFE0_0000h FFFF_FFFFh)
>>   The top 2 Mbytes of the Extended Memory Region is reserved for System
>>   BIOS (High BIOS), extended BIOS for PCI devices, and the A20 alias of
>>   the system BIOS. The CPU begins execution from the High BIOS after
>>   reset. This region is mapped to the PCI so that the upper subset of
>>   this region is aliased to 16 Mbytes minus 256-Kbyte range.
>> 
> 
> That is presumably a 286 compatibility hack -- the 286 had 24 address 
> lines.  I doubt anyone gives a hoot about it, and neither EDK2 nor 
> SeaBIOS should care.
> 
> 	-hpa
> 
> -- 
> H. Peter Anvin, Intel Open Source Technology Center
> I work for Intel.  I don't speak on their behalf.
> 


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