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EDK2 doxygen online documents - Firmware Encoding Index

UefiCpuPkg/Include/Register/LocalApic.h

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00001 
00015 #ifndef __LOCAL_APIC_H__
00016 #define __LOCAL_APIC_H__
00017 
00018 //
00019 // Definitions for IA32 architectural MSRs
00020 //
00021 #define MSR_IA32_APIC_BASE_ADDRESS              0x1B
00022 
00023 //
00024 // Definitions for CPUID instruction
00025 //
00026 #define CPUID_VERSION_INFO                      0x1
00027 #define CPUID_EXTENDED_FUNCTION                 0x80000000
00028 #define CPUID_VIR_PHY_ADDRESS_SIZE              0x80000008
00029 
00030 //
00031 // Definition for Local APIC registers and related values
00032 //
00033 #define XAPIC_ID_OFFSET                         0x20
00034 #define XAPIC_VERSION_OFFSET                    0x30
00035 #define XAPIC_EOI_OFFSET                        0x0b0
00036 #define XAPIC_ICR_DFR_OFFSET                    0x0e0
00037 #define XAPIC_SPURIOUS_VECTOR_OFFSET            0x0f0
00038 #define XAPIC_ICR_LOW_OFFSET                    0x300
00039 #define XAPIC_ICR_HIGH_OFFSET                   0x310
00040 #define XAPIC_LVT_TIMER_OFFSET                  0x320
00041 #define XAPIC_LVT_LINT0_OFFSET                  0x350
00042 #define XAPIC_LVT_LINT1_OFFSET                  0x360
00043 #define XAPIC_TIMER_INIT_COUNT_OFFSET           0x380
00044 #define XAPIC_TIMER_CURRENT_COUNT_OFFSET        0x390
00045 #define XAPIC_TIMER_DIVIDE_CONFIGURATION_OFFSET 0x3E0
00046 
00047 #define X2APIC_MSR_BASE_ADDRESS                 0x800
00048 #define X2APIC_MSR_ICR_ADDRESS                  0x830
00049 
00050 #define LOCAL_APIC_DELIVERY_MODE_FIXED           0
00051 #define LOCAL_APIC_DELIVERY_MODE_LOWEST_PRIORITY 1
00052 #define LOCAL_APIC_DELIVERY_MODE_SMI             2
00053 #define LOCAL_APIC_DELIVERY_MODE_NMI             4
00054 #define LOCAL_APIC_DELIVERY_MODE_INIT            5
00055 #define LOCAL_APIC_DELIVERY_MODE_STARTUP         6
00056 #define LOCAL_APIC_DELIVERY_MODE_EXTINT          7
00057 
00058 #define LOCAL_APIC_DESTINATION_SHORTHAND_NO_SHORTHAND       0
00059 #define LOCAL_APIC_DESTINATION_SHORTHAND_SELF               1
00060 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_INCLUDING_SELF 2
00061 #define LOCAL_APIC_DESTINATION_SHORTHAND_ALL_EXCLUDING_SELF 3
00062 
00063 typedef union {
00064   struct {
00065     UINT32  Reserved0:8;     
00066     UINT32  Bsp:1;           
00067     UINT32  Reserved1:1;     
00068     UINT32  Extd:1;          
00069     UINT32  En:1;            
00070     UINT32  ApicBaseLow:20;  
00071     UINT32  ApicBaseHigh:32;
00072   } Bits;
00073   UINT64    Uint64;
00074 } MSR_IA32_APIC_BASE;
00075 
00076 //
00077 // Local APIC Version Register.
00078 //
00079 typedef union {
00080   struct {
00081     UINT32  Version:8;                  
00082     UINT32  Reserved0:8;                
00083     UINT32  MaxLvtEntry:8;              
00084     UINT32  EoiBroadcastSuppression:1;  
00085     UINT32  Reserved1:7;                
00086   } Bits;
00087   UINT32    Uint32;
00088 } LOCAL_APIC_VERSION;
00089 
00090 //
00091 // Low half of Interrupt Command Register (ICR).
00092 //
00093 typedef union {
00094   struct {
00095     UINT32  Vector:8;                
00096     UINT32  DeliveryMode:3;          
00097     UINT32  DestinationMode:1;       
00098     UINT32  DeliveryStatus:1;        
00099     UINT32  Reserved0:1;             
00100     UINT32  Level:1;                 
00101     UINT32  TriggerMode:1;           
00102     UINT32  Reserved1:2;             
00103     UINT32  DestinationShorthand:2;  
00104     UINT32  Reserved2:12;            
00105   } Bits;
00106   UINT32    Uint32;
00107 } LOCAL_APIC_ICR_LOW;
00108 
00109 //
00110 // High half of Interrupt Command Register (ICR)
00111 //
00112 typedef union {
00113   struct {
00114     UINT32  Reserved0:24;   
00115     UINT32  Destination:8;  
00116   } Bits;
00117   UINT32    Uint32;         
00118 } LOCAL_APIC_ICR_HIGH;
00119 
00120 //
00121 // Spurious-Interrupt Vector Register (SVR)
00122 //
00123 typedef union {
00124   struct {
00125     UINT32  SpuriousVector:8;           
00126     UINT32  SoftwareEnable:1;           
00127     UINT32  FocusProcessorChecking:1;   
00128     UINT32  Reserved0:2;                
00129     UINT32  EoiBroadcastSuppression:1;  
00130     UINT32  Reserved1:19;               
00131   } Bits;
00132   UINT32    Uint32;
00133 } LOCAL_APIC_SVR;
00134 
00135 //
00136 // Divide Configuration Register (DCR)
00137 //
00138 typedef union {
00139   struct {
00140     UINT32  DivideValue1:2;  
00141     UINT32  Reserved0:1;     
00142     UINT32  DivideValue2:1;  
00143     UINT32  Reserved1:28;    
00144   } Bits;
00145   UINT32    Uint32;
00146 } LOCAL_APIC_DCR;
00147 
00148 //
00149 // LVT Timer Register
00150 //
00151 typedef union {
00152   struct {
00153     UINT32  Vector:8;          
00154     UINT32  Reserved0:4;       
00155     UINT32  DeliveryStatus:1;  
00156     UINT32  Reserved1:3;       
00157     UINT32  Mask:1;            
00158     UINT32  TimerMode:1;       
00159     UINT32  Reserved2:14;      
00160   } Bits;
00161   UINT32    Uint32;
00162 } LOCAL_APIC_LVT_TIMER;
00163 
00164 //
00165 // LVT LINT0/LINT1 Register
00166 //
00167 typedef union {
00168   struct {
00169     UINT32  Vector:8;            
00170     UINT32  DeliveryMode:3;      
00171     UINT32  Reserved0:1;         
00172     UINT32  DeliveryStatus:1;    
00173     UINT32  InputPinPolarity:1;  
00174     UINT32  RemoteIrr:1;         
00175     UINT32  TriggerMode:1;       
00176     UINT32  Mask:1;              
00177     UINT32  Reserved1:15;        
00178   } Bits;
00179   UINT32    Uint32;
00180 } LOCAL_APIC_LVT_LINT;
00181 
00182 //
00183 // MSI Address Register
00184 //
00185 typedef union {
00186   struct {
00187     UINT32  Reserved0:2;         
00188     UINT32  DestinationMode:1;   
00189     UINT32  RedirectionHint:1;   
00190     UINT32  Reserved1:8;         
00191     UINT32  DestinationId:8;     
00192     UINT32  BaseAddress:12;      
00193   } Bits;
00194   UINT32    Uint32;
00195 } LOCAL_APIC_MSI_ADDRESS;
00196 
00197 //
00198 // MSI Address Register
00199 //
00200 typedef union {
00201   struct {
00202     UINT32  Vector:8;            
00203     UINT32  DeliveryMode:3;      
00204     UINT32  Reserved0:3;         
00205     UINT32  Level:1;             
00206     UINT32  TriggerMode:1;       
00207     UINT32  Reserved1:16;        
00208     UINT32  Reserved2:32;        
00209   } Bits;
00210   UINT64    Uint64;
00211 } LOCAL_APIC_MSI_DATA;
00212 
00213 #endif
00214 
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