EDK2 doxygen online documents - Firmware Encoding Index 1
EDK2 doxygen online documents - Firmware Encoding Index

MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h

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00001 
00016 #ifndef _EFI_PCI_BUS_H_
00017 #define _EFI_PCI_BUS_H_
00018 
00019 #include <PiDxe.h>
00020 
00021 #include <Protocol/LoadedImage.h>
00022 #include <Protocol/PciHostBridgeResourceAllocation.h>
00023 #include <Protocol/PciIo.h>
00024 #include <Protocol/LoadFile2.h>
00025 #include <Protocol/PciRootBridgeIo.h>
00026 #include <Protocol/PciHotPlugRequest.h>
00027 #include <Protocol/DevicePath.h>
00028 #include <Protocol/PciPlatform.h>
00029 #include <Protocol/PciHotPlugInit.h>
00030 #include <Protocol/Decompress.h>
00031 #include <Protocol/BusSpecificDriverOverride.h>
00032 #include <Protocol/IncompatiblePciDeviceSupport.h>
00033 #include <Protocol/PciOverride.h>
00034 #include <Protocol/PciEnumerationComplete.h>
00035 #include <Protocol/DevicePathToText.h>
00036 
00037 #include <Library/DebugLib.h>
00038 #include <Library/UefiDriverEntryPoint.h>
00039 #include <Library/BaseLib.h>
00040 #include <Library/UefiLib.h>
00041 #include <Library/BaseMemoryLib.h>
00042 #include <Library/ReportStatusCodeLib.h>
00043 #include <Library/MemoryAllocationLib.h>
00044 #include <Library/UefiBootServicesTableLib.h>
00045 #include <Library/DevicePathLib.h>
00046 #include <Library/PcdLib.h>
00047 #include <Library/PeCoffLib.h>
00048 
00049 #include <IndustryStandard/Pci.h>
00050 #include <IndustryStandard/PeImage.h>
00051 #include <IndustryStandard/Acpi.h>
00052 
00053 typedef struct _PCI_IO_DEVICE              PCI_IO_DEVICE;
00054 typedef struct _PCI_BAR                    PCI_BAR;
00055 
00056 #define EFI_PCI_RID(Bus, Device, Function)  (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
00057 #define EFI_PCI_BUS_OF_RID(RID)             ((UINT32)RID >> 8)
00058 
00059 #define     EFI_PCI_IOV_POLICY_ARI           0x0001
00060 #define     EFI_PCI_IOV_POLICY_SRIOV         0x0002
00061 #define     EFI_PCI_IOV_POLICY_MRIOV         0x0004
00062 
00063 typedef enum {
00064   PciBarTypeUnknown = 0,
00065   PciBarTypeIo16,
00066   PciBarTypeIo32,
00067   PciBarTypeMem32,
00068   PciBarTypePMem32,
00069   PciBarTypeMem64,
00070   PciBarTypePMem64,
00071   PciBarTypeIo,
00072   PciBarTypeMem,
00073   PciBarTypeMaxType
00074 } PCI_BAR_TYPE;
00075 
00076 #include "ComponentName.h"
00077 #include "PciIo.h"
00078 #include "PciCommand.h"
00079 #include "PciDeviceSupport.h"
00080 #include "PciEnumerator.h"
00081 #include "PciEnumeratorSupport.h"
00082 #include "PciDriverOverride.h"
00083 #include "PciRomTable.h"
00084 #include "PciOptionRomSupport.h"
00085 #include "PciPowerManagement.h"
00086 #include "PciHotPlugSupport.h"
00087 #include "PciLib.h"
00088 
00089 #define VGABASE1  0x3B0
00090 #define VGALIMIT1 0x3BB
00091 
00092 #define VGABASE2  0x3C0
00093 #define VGALIMIT2 0x3DF
00094 
00095 #define ISABASE   0x100
00096 #define ISALIMIT  0x3FF
00097 
00098 //
00099 // PCI BAR parameters
00100 //
00101 struct _PCI_BAR {
00102   UINT64        BaseAddress;
00103   UINT64        Length;
00104   UINT64        Alignment;
00105   PCI_BAR_TYPE  BarType;
00106   BOOLEAN       Prefetchable;
00107   UINT8         MemType;
00108   UINT16        Offset;
00109 };
00110 
00111 //
00112 // defined in PCI Card Specification, 8.0
00113 //
00114 #define PCI_CARD_MEMORY_BASE_0                0x1C
00115 #define PCI_CARD_MEMORY_LIMIT_0               0x20
00116 #define PCI_CARD_MEMORY_BASE_1                0x24
00117 #define PCI_CARD_MEMORY_LIMIT_1               0x28
00118 #define PCI_CARD_IO_BASE_0_LOWER              0x2C
00119 #define PCI_CARD_IO_BASE_0_UPPER              0x2E
00120 #define PCI_CARD_IO_LIMIT_0_LOWER             0x30
00121 #define PCI_CARD_IO_LIMIT_0_UPPER             0x32
00122 #define PCI_CARD_IO_BASE_1_LOWER              0x34
00123 #define PCI_CARD_IO_BASE_1_UPPER              0x36
00124 #define PCI_CARD_IO_LIMIT_1_LOWER             0x38
00125 #define PCI_CARD_IO_LIMIT_1_UPPER             0x3A
00126 #define PCI_CARD_BRIDGE_CONTROL               0x3E
00127 
00128 #define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE BIT8
00129 #define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE BIT9
00130 
00131 #define RB_IO_RANGE                           1
00132 #define RB_MEM32_RANGE                        2
00133 #define RB_PMEM32_RANGE                       3
00134 #define RB_MEM64_RANGE                        4
00135 #define RB_PMEM64_RANGE                       5
00136 
00137 #define PPB_BAR_0                             0
00138 #define PPB_BAR_1                             1
00139 #define PPB_IO_RANGE                          2
00140 #define PPB_MEM32_RANGE                       3
00141 #define PPB_PMEM32_RANGE                      4
00142 #define PPB_PMEM64_RANGE                      5
00143 #define PPB_MEM64_RANGE                       0xFF
00144 
00145 #define P2C_BAR_0                             0
00146 #define P2C_MEM_1                             1
00147 #define P2C_MEM_2                             2
00148 #define P2C_IO_1                              3
00149 #define P2C_IO_2                              4
00150 
00151 #define EFI_BRIDGE_IO32_DECODE_SUPPORTED      0x0001
00152 #define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED    0x0002
00153 #define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED    0x0004
00154 #define EFI_BRIDGE_IO16_DECODE_SUPPORTED      0x0008
00155 #define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED 0x0010
00156 #define EFI_BRIDGE_MEM64_DECODE_SUPPORTED     0x0020
00157 #define EFI_BRIDGE_MEM32_DECODE_SUPPORTED     0x0040
00158 
00159 #define PCI_MAX_HOST_BRIDGE_NUM               0x0010
00160 
00161 //
00162 // Define option for attribute
00163 //
00164 #define EFI_SET_SUPPORTS    0
00165 #define EFI_SET_ATTRIBUTES  1
00166 
00167 #define PCI_IO_DEVICE_SIGNATURE               SIGNATURE_32 ('p', 'c', 'i', 'o')
00168 
00169 struct _PCI_IO_DEVICE {
00170   UINT32                                    Signature;
00171   EFI_HANDLE                                Handle;
00172   EFI_PCI_IO_PROTOCOL                       PciIo;
00173   LIST_ENTRY                                Link;
00174 
00175   EFI_BUS_SPECIFIC_DRIVER_OVERRIDE_PROTOCOL PciDriverOverride;
00176   EFI_DEVICE_PATH_PROTOCOL                  *DevicePath;
00177   EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL           *PciRootBridgeIo;
00178   EFI_LOAD_FILE2_PROTOCOL                   LoadFile2;
00179 
00180   //
00181   // PCI configuration space header type
00182   //
00183   PCI_TYPE00                                Pci;
00184 
00185   //
00186   // Bus number, Device number, Function number
00187   //
00188   UINT8                                     BusNumber;
00189   UINT8                                     DeviceNumber;
00190   UINT8                                     FunctionNumber;
00191 
00192   //
00193   // BAR for this PCI Device
00194   //
00195   PCI_BAR                                   PciBar[PCI_MAX_BAR];
00196 
00197   //
00198   // The bridge device this pci device is subject to
00199   //
00200   PCI_IO_DEVICE                             *Parent;
00201 
00202   //
00203   // A linked list for children Pci Device if it is bridge device
00204   //
00205   LIST_ENTRY                                ChildList;
00206 
00207   //
00208   // TURE if the PCI bus driver creates the handle for this PCI device
00209   //
00210   BOOLEAN                                   Registered;
00211 
00212   //
00213   // TRUE if the PCI bus driver successfully allocates the resource required by
00214   // this PCI device
00215   //
00216   BOOLEAN                                   Allocated;
00217 
00218   //
00219   // The attribute this PCI device currently set
00220   //
00221   UINT64                                    Attributes;
00222 
00223   //
00224   // The attributes this PCI device actually supports
00225   //
00226   UINT64                                    Supports;
00227 
00228   //
00229   // The resource decode the bridge supports
00230   //
00231   UINT32                                    Decodes;
00232 
00233   //
00234   // TRUE if the ROM image is from the PCI Option ROM BAR
00235   //
00236   BOOLEAN                                   EmbeddedRom;
00237 
00238   //
00239   // The OptionRom Size
00240   //
00241   UINT64                                    RomSize;
00242 
00243   //
00244   // The OptionRom Size
00245   //
00246   UINT64                                    RomBase;
00247 
00248   //
00249   // TRUE if all OpROM (in device or in platform specific position) have been processed
00250   //
00251   BOOLEAN                                   AllOpRomProcessed;
00252 
00253   //
00254   // TRUE if there is any EFI driver in the OptionRom
00255   //
00256   BOOLEAN                                   BusOverride;
00257 
00258   //
00259   // A list tracking reserved resource on a bridge device
00260   //
00261   LIST_ENTRY                                ReservedResourceList;
00262 
00263   //
00264   // A list tracking image handle of platform specific overriding driver
00265   //
00266   LIST_ENTRY                                OptionRomDriverList;
00267 
00268   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *ResourcePaddingDescriptors;
00269   EFI_HPC_PADDING_ATTRIBUTES                PaddingAttributes;
00270 
00271   //
00272   // Bus number ranges for a PCI Root Bridge device
00273   //
00274   EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR         *BusNumberRanges;
00275 
00276   BOOLEAN                                   IsPciExp;
00277   //
00278   // For SR-IOV
00279   //
00280   UINT8                                     PciExpressCapabilityOffset;
00281   UINT32                                    AriCapabilityOffset;
00282   UINT32                                    SrIovCapabilityOffset;
00283   UINT32                                    MrIovCapabilityOffset;
00284   PCI_BAR                                   VfPciBar[PCI_MAX_BAR];
00285   UINT32                                    SystemPageSize;
00286   UINT16                                    InitialVFs;
00287   UINT16                                    ReservedBusNum;
00288   //
00289   // Per PCI to PCI Bridge spec, I/O window is 4K aligned,
00290   // but some chipsets support non-stardard I/O window aligments less than 4K.
00291   // This field is used to support this case.
00292   //
00293   UINT16                                    BridgeIoAlignment;
00294 };
00295 
00296 #define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a) \
00297   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
00298 
00299 #define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a) \
00300   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
00301 
00302 #define PCI_IO_DEVICE_FROM_LINK(a) \
00303   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
00304 
00305 #define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a) \
00306   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
00307 
00308 
00309 
00310 //
00311 // Global Variables
00312 //
00313 extern EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *gEfiIncompatiblePciDeviceSupport;
00314 extern EFI_DRIVER_BINDING_PROTOCOL                  gPciBusDriverBinding;
00315 extern EFI_COMPONENT_NAME_PROTOCOL                  gPciBusComponentName;
00316 extern EFI_COMPONENT_NAME2_PROTOCOL                 gPciBusComponentName2;
00317 extern BOOLEAN                                      gFullEnumeration;
00318 extern UINTN                                        gPciHostBridgeNumber;
00319 extern EFI_HANDLE                                   gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM];
00320 extern UINT64                                       gAllOne;
00321 extern UINT64                                       gAllZero;
00322 extern EFI_PCI_PLATFORM_PROTOCOL                    *gPciPlatformProtocol;
00323 extern EFI_PCI_OVERRIDE_PROTOCOL                    *gPciOverrideProtocol;
00324 extern BOOLEAN                                      mReserveIsaAliases;
00325 extern BOOLEAN                                      mReserveVgaAliases;
00326 
00336 #define IS_PCI_GFX(_p)     IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)
00337 
00352 EFI_STATUS
00353 EFIAPI
00354 PciBusDriverBindingSupported (
00355   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
00356   IN EFI_HANDLE                     Controller,
00357   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
00358   );
00359 
00374 EFI_STATUS
00375 EFIAPI
00376 PciBusDriverBindingStart (
00377   IN EFI_DRIVER_BINDING_PROTOCOL    *This,
00378   IN EFI_HANDLE                     Controller,
00379   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath
00380   );
00381 
00396 EFI_STATUS
00397 EFIAPI
00398 PciBusDriverBindingStop (
00399   IN  EFI_DRIVER_BINDING_PROTOCOL   *This,
00400   IN  EFI_HANDLE                    Controller,
00401   IN  UINTN                         NumberOfChildren,
00402   IN  EFI_HANDLE                    *ChildHandleBuffer
00403   );
00404 
00405 #endif
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