EDK2 doxygen online documents - Firmware Encoding Index 1
EDK2 doxygen online documents - Firmware Encoding Index
Data Structures | Defines | Typedefs | Enumerations | Functions | Variables

MdeModulePkg/Bus/Pci/PciBusDxe/PciBus.h File Reference

#include <PiDxe.h>
#include <Protocol/LoadedImage.h>
#include <Protocol/PciHostBridgeResourceAllocation.h>
#include <Protocol/PciIo.h>
#include <Protocol/LoadFile2.h>
#include <Protocol/PciRootBridgeIo.h>
#include <Protocol/PciHotPlugRequest.h>
#include <Protocol/DevicePath.h>
#include <Protocol/PciPlatform.h>
#include <Protocol/PciHotPlugInit.h>
#include <Protocol/Decompress.h>
#include <Protocol/BusSpecificDriverOverride.h>
#include <Protocol/IncompatiblePciDeviceSupport.h>
#include <Protocol/PciOverride.h>
#include <Protocol/PciEnumerationComplete.h>
#include <Protocol/DevicePathToText.h>
#include <Library/DebugLib.h>
#include <Library/UefiDriverEntryPoint.h>
#include <Library/BaseLib.h>
#include <Library/UefiLib.h>
#include <Library/BaseMemoryLib.h>
#include <Library/ReportStatusCodeLib.h>
#include <Library/MemoryAllocationLib.h>
#include <Library/UefiBootServicesTableLib.h>
#include <Library/DevicePathLib.h>
#include <Library/PcdLib.h>
#include <Library/PeCoffLib.h>
#include <IndustryStandard/Pci.h>
#include <IndustryStandard/PeImage.h>
#include <IndustryStandard/Acpi.h>
#include "ComponentName.h"
#include "PciIo.h"
#include "PciCommand.h"
#include "PciDeviceSupport.h"
#include "PciEnumerator.h"
#include "PciEnumeratorSupport.h"
#include "PciDriverOverride.h"
#include "PciRomTable.h"
#include "PciOptionRomSupport.h"
#include "PciPowerManagement.h"
#include "PciHotPlugSupport.h"
#include "PciLib.h"

Go to the source code of this file.

Data Structures

struct  _PCI_BAR
struct  _PCI_IO_DEVICE

Defines

#define EFI_PCI_RID(Bus, Device, Function)   (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)
#define EFI_PCI_BUS_OF_RID(RID)   ((UINT32)RID >> 8)
#define EFI_PCI_IOV_POLICY_ARI   0x0001
#define EFI_PCI_IOV_POLICY_SRIOV   0x0002
#define EFI_PCI_IOV_POLICY_MRIOV   0x0004
#define VGABASE1   0x3B0
#define VGALIMIT1   0x3BB
#define VGABASE2   0x3C0
#define VGALIMIT2   0x3DF
#define ISABASE   0x100
#define ISALIMIT   0x3FF
#define PCI_CARD_MEMORY_BASE_0   0x1C
#define PCI_CARD_MEMORY_LIMIT_0   0x20
#define PCI_CARD_MEMORY_BASE_1   0x24
#define PCI_CARD_MEMORY_LIMIT_1   0x28
#define PCI_CARD_IO_BASE_0_LOWER   0x2C
#define PCI_CARD_IO_BASE_0_UPPER   0x2E
#define PCI_CARD_IO_LIMIT_0_LOWER   0x30
#define PCI_CARD_IO_LIMIT_0_UPPER   0x32
#define PCI_CARD_IO_BASE_1_LOWER   0x34
#define PCI_CARD_IO_BASE_1_UPPER   0x36
#define PCI_CARD_IO_LIMIT_1_LOWER   0x38
#define PCI_CARD_IO_LIMIT_1_UPPER   0x3A
#define PCI_CARD_BRIDGE_CONTROL   0x3E
#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE   BIT8
#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE   BIT9
#define RB_IO_RANGE   1
#define RB_MEM32_RANGE   2
#define RB_PMEM32_RANGE   3
#define RB_MEM64_RANGE   4
#define RB_PMEM64_RANGE   5
#define PPB_BAR_0   0
#define PPB_BAR_1   1
#define PPB_IO_RANGE   2
#define PPB_MEM32_RANGE   3
#define PPB_PMEM32_RANGE   4
#define PPB_PMEM64_RANGE   5
#define PPB_MEM64_RANGE   0xFF
#define P2C_BAR_0   0
#define P2C_MEM_1   1
#define P2C_MEM_2   2
#define P2C_IO_1   3
#define P2C_IO_2   4
#define EFI_BRIDGE_IO32_DECODE_SUPPORTED   0x0001
#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED   0x0002
#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED   0x0004
#define EFI_BRIDGE_IO16_DECODE_SUPPORTED   0x0008
#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED   0x0010
#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED   0x0020
#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED   0x0040
#define PCI_MAX_HOST_BRIDGE_NUM   0x0010
#define EFI_SET_SUPPORTS   0
#define EFI_SET_ATTRIBUTES   1
#define PCI_IO_DEVICE_SIGNATURE   SIGNATURE_32 ('p', 'c', 'i', 'o')
#define PCI_IO_DEVICE_FROM_PCI_IO_THIS(a)   CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)
#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS(a)   CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)
#define PCI_IO_DEVICE_FROM_LINK(a)   CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)
#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS(a)   CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)
#define IS_PCI_GFX(_p)   IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)

Typedefs

typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE
typedef struct _PCI_BAR PCI_BAR

Enumerations

enum  PCI_BAR_TYPE {
  PciBarTypeUnknown = 0, PciBarTypeIo16, PciBarTypeIo32, PciBarTypeMem32,
  PciBarTypePMem32, PciBarTypeMem64, PciBarTypePMem64, PciBarTypeIo,
  PciBarTypeMem, PciBarTypeMaxType, PciBarTypeUnknown = 0, PciBarTypeIo16,
  PciBarTypeIo32, PciBarTypeMem32, PciBarTypePMem32, PciBarTypeMem64,
  PciBarTypePMem64, PciBarTypeIo, PciBarTypeMem, PciBarTypeMaxType
}

Functions

EFI_STATUS EFIAPI PciBusDriverBindingSupported (IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath)
EFI_STATUS EFIAPI PciBusDriverBindingStart (IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, IN EFI_DEVICE_PATH_PROTOCOL *RemainingDevicePath)
EFI_STATUS EFIAPI PciBusDriverBindingStop (IN EFI_DRIVER_BINDING_PROTOCOL *This, IN EFI_HANDLE Controller, IN UINTN NumberOfChildren, IN EFI_HANDLE *ChildHandleBuffer)

Variables

EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOLgEfiIncompatiblePciDeviceSupport
EFI_DRIVER_BINDING_PROTOCOL gPciBusDriverBinding
EFI_COMPONENT_NAME_PROTOCOL gPciBusComponentName
EFI_COMPONENT_NAME2_PROTOCOL gPciBusComponentName2
BOOLEAN gFullEnumeration
UINTN gPciHostBridgeNumber
EFI_HANDLE gPciHostBrigeHandles [PCI_MAX_HOST_BRIDGE_NUM]
UINT64 gAllOne
UINT64 gAllZero
EFI_PCI_PLATFORM_PROTOCOLgPciPlatformProtocol
EFI_PCI_OVERRIDE_PROTOCOLgPciOverrideProtocol
BOOLEAN mReserveIsaAliases
BOOLEAN mReserveVgaAliases

Detailed Description

Header files and data structures needed by PCI Bus module.

Copyright (c) 2006 - 2011, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file PciBus.h.


Define Documentation

#define EFI_BRIDGE_IO16_DECODE_SUPPORTED   0x0008

Definition at line 154 of file PciBus.h.

#define EFI_BRIDGE_IO32_DECODE_SUPPORTED   0x0001

Definition at line 151 of file PciBus.h.

#define EFI_BRIDGE_MEM32_DECODE_SUPPORTED   0x0040

Definition at line 157 of file PciBus.h.

#define EFI_BRIDGE_MEM64_DECODE_SUPPORTED   0x0020

Definition at line 156 of file PciBus.h.

#define EFI_BRIDGE_PMEM32_DECODE_SUPPORTED   0x0002

Definition at line 152 of file PciBus.h.

#define EFI_BRIDGE_PMEM64_DECODE_SUPPORTED   0x0004

Definition at line 153 of file PciBus.h.

#define EFI_BRIDGE_PMEM_MEM_COMBINE_SUPPORTED   0x0010

Definition at line 155 of file PciBus.h.

#define EFI_PCI_BUS_OF_RID (   RID)    ((UINT32)RID >> 8)

Definition at line 57 of file PciBus.h.

#define EFI_PCI_IOV_POLICY_ARI   0x0001

Definition at line 59 of file PciBus.h.

#define EFI_PCI_IOV_POLICY_MRIOV   0x0004

Definition at line 61 of file PciBus.h.

#define EFI_PCI_IOV_POLICY_SRIOV   0x0002

Definition at line 60 of file PciBus.h.

#define EFI_PCI_RID (   Bus,
  Device,
  Function 
)    (((UINT32)Bus << 8) + ((UINT32)Device << 3) + (UINT32)Function)

Definition at line 56 of file PciBus.h.

#define EFI_SET_ATTRIBUTES   1

Definition at line 165 of file PciBus.h.

#define EFI_SET_SUPPORTS   0

Definition at line 164 of file PciBus.h.

#define IS_PCI_GFX (   _p)    IS_CLASS2 (_p, PCI_CLASS_DISPLAY, PCI_CLASS_DISPLAY_OTHER)

Macro that checks whether device is a GFX device.

Parameters:
_pSpecified device.
Return values:
TRUEDevice is a a GFX device.
FALSEDevice is not a a GFX device.

Definition at line 336 of file PciBus.h.

#define ISABASE   0x100

Definition at line 95 of file PciBus.h.

#define ISALIMIT   0x3FF

Definition at line 96 of file PciBus.h.

#define P2C_BAR_0   0

Definition at line 145 of file PciBus.h.

#define P2C_IO_1   3

Definition at line 148 of file PciBus.h.

#define P2C_IO_2   4

Definition at line 149 of file PciBus.h.

#define P2C_MEM_1   1

Definition at line 146 of file PciBus.h.

#define P2C_MEM_2   2

Definition at line 147 of file PciBus.h.

#define PCI_CARD_BRIDGE_CONTROL   0x3E

Definition at line 126 of file PciBus.h.

#define PCI_CARD_IO_BASE_0_LOWER   0x2C

Definition at line 118 of file PciBus.h.

#define PCI_CARD_IO_BASE_0_UPPER   0x2E

Definition at line 119 of file PciBus.h.

#define PCI_CARD_IO_BASE_1_LOWER   0x34

Definition at line 122 of file PciBus.h.

#define PCI_CARD_IO_BASE_1_UPPER   0x36

Definition at line 123 of file PciBus.h.

#define PCI_CARD_IO_LIMIT_0_LOWER   0x30

Definition at line 120 of file PciBus.h.

#define PCI_CARD_IO_LIMIT_0_UPPER   0x32

Definition at line 121 of file PciBus.h.

#define PCI_CARD_IO_LIMIT_1_LOWER   0x38

Definition at line 124 of file PciBus.h.

#define PCI_CARD_IO_LIMIT_1_UPPER   0x3A

Definition at line 125 of file PciBus.h.

#define PCI_CARD_MEMORY_BASE_0   0x1C

Definition at line 114 of file PciBus.h.

#define PCI_CARD_MEMORY_BASE_1   0x24

Definition at line 116 of file PciBus.h.

#define PCI_CARD_MEMORY_LIMIT_0   0x20

Definition at line 115 of file PciBus.h.

#define PCI_CARD_MEMORY_LIMIT_1   0x28

Definition at line 117 of file PciBus.h.

#define PCI_CARD_PREFETCHABLE_MEMORY_0_ENABLE   BIT8

Definition at line 128 of file PciBus.h.

#define PCI_CARD_PREFETCHABLE_MEMORY_1_ENABLE   BIT9

Definition at line 129 of file PciBus.h.

#define PCI_IO_DEVICE_FROM_LINK (   a)    CR (a, PCI_IO_DEVICE, Link, PCI_IO_DEVICE_SIGNATURE)

Definition at line 302 of file PciBus.h.

#define PCI_IO_DEVICE_FROM_LOAD_FILE2_THIS (   a)    CR (a, PCI_IO_DEVICE, LoadFile2, PCI_IO_DEVICE_SIGNATURE)

Definition at line 305 of file PciBus.h.

#define PCI_IO_DEVICE_FROM_PCI_DRIVER_OVERRIDE_THIS (   a)    CR (a, PCI_IO_DEVICE, PciDriverOverride, PCI_IO_DEVICE_SIGNATURE)

Definition at line 299 of file PciBus.h.

#define PCI_IO_DEVICE_FROM_PCI_IO_THIS (   a)    CR (a, PCI_IO_DEVICE, PciIo, PCI_IO_DEVICE_SIGNATURE)

Definition at line 296 of file PciBus.h.

#define PCI_IO_DEVICE_SIGNATURE   SIGNATURE_32 ('p', 'c', 'i', 'o')

Definition at line 167 of file PciBus.h.

#define PCI_MAX_HOST_BRIDGE_NUM   0x0010

Definition at line 159 of file PciBus.h.

#define PPB_BAR_0   0

Definition at line 137 of file PciBus.h.

#define PPB_BAR_1   1

Definition at line 138 of file PciBus.h.

#define PPB_IO_RANGE   2

Definition at line 139 of file PciBus.h.

#define PPB_MEM32_RANGE   3

Definition at line 140 of file PciBus.h.

#define PPB_MEM64_RANGE   0xFF

Definition at line 143 of file PciBus.h.

#define PPB_PMEM32_RANGE   4

Definition at line 141 of file PciBus.h.

#define PPB_PMEM64_RANGE   5

Definition at line 142 of file PciBus.h.

#define RB_IO_RANGE   1

Definition at line 131 of file PciBus.h.

#define RB_MEM32_RANGE   2

Definition at line 132 of file PciBus.h.

#define RB_MEM64_RANGE   4

Definition at line 134 of file PciBus.h.

#define RB_PMEM32_RANGE   3

Definition at line 133 of file PciBus.h.

#define RB_PMEM64_RANGE   5

Definition at line 135 of file PciBus.h.

#define VGABASE1   0x3B0

Definition at line 89 of file PciBus.h.

#define VGABASE2   0x3C0

Definition at line 92 of file PciBus.h.

#define VGALIMIT1   0x3BB

Definition at line 90 of file PciBus.h.

#define VGALIMIT2   0x3DF

Definition at line 93 of file PciBus.h.


Typedef Documentation

typedef struct _PCI_BAR PCI_BAR

Definition at line 54 of file PciBus.h.

typedef struct _PCI_IO_DEVICE PCI_IO_DEVICE

Definition at line 53 of file PciBus.h.


Enumeration Type Documentation

Enumerator:
PciBarTypeUnknown 
PciBarTypeIo16 
PciBarTypeIo32 
PciBarTypeMem32 
PciBarTypePMem32 
PciBarTypeMem64 
PciBarTypePMem64 
PciBarTypeIo 
PciBarTypeMem 
PciBarTypeMaxType 
PciBarTypeUnknown 
PciBarTypeIo16 
PciBarTypeIo32 
PciBarTypeMem32 
PciBarTypePMem32 
PciBarTypeMem64 
PciBarTypePMem64 
PciBarTypeIo 
PciBarTypeMem 
PciBarTypeMaxType 

Definition at line 63 of file PciBus.h.


Function Documentation

EFI_STATUS EFIAPI PciBusDriverBindingStart ( IN EFI_DRIVER_BINDING_PROTOCOL This,
IN EFI_HANDLE  Controller,
IN EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath 
)

Start this driver on ControllerHandle and enumerate Pci bus and start all device under PCI bus.

Parameters:
ThisProtocol instance pointer.
ControllerHandle of device to bind driver to.
RemainingDevicePathOptional parameter use to pick a specific child. device to start.
Return values:
EFI_SUCCESSThis driver is added to ControllerHandle.
EFI_ALREADY_STARTEDThis driver is already running on ControllerHandle.
otherThis driver does not support this device.

Definition at line 223 of file PciBus.c.

EFI_STATUS EFIAPI PciBusDriverBindingStop ( IN EFI_DRIVER_BINDING_PROTOCOL This,
IN EFI_HANDLE  Controller,
IN UINTN  NumberOfChildren,
IN EFI_HANDLE ChildHandleBuffer 
)

Stop this driver on ControllerHandle. Support stoping any child handles created by this driver.

Parameters:
ThisProtocol instance pointer.
ControllerHandle of device to stop driver on.
NumberOfChildrenNumber of Handles in ChildHandleBuffer. If number of children is zero stop the entire bus driver.
ChildHandleBufferList of Child Handles to Stop.
Return values:
EFI_SUCCESSThis driver is removed ControllerHandle.
otherThis driver was not removed from this device.

Definition at line 270 of file PciBus.c.

EFI_STATUS EFIAPI PciBusDriverBindingSupported ( IN EFI_DRIVER_BINDING_PROTOCOL This,
IN EFI_HANDLE  Controller,
IN EFI_DEVICE_PATH_PROTOCOL RemainingDevicePath 
)

Test to see if this driver supports ControllerHandle. Any ControllerHandle than contains a gEfiPciRootBridgeIoProtocolGuid protocol can be supported.

Parameters:
ThisProtocol instance pointer.
ControllerHandle of device to test.
RemainingDevicePathOptional parameter use to pick a specific child. device to start.
Return values:
EFI_SUCCESSThis driver supports this device.
EFI_ALREADY_STARTEDThis driver is already running on this device.
otherThis driver does not support this device.

Definition at line 133 of file PciBus.c.


Variable Documentation

Definition at line 78 of file PciBus.c.

Definition at line 79 of file PciBus.c.

Definition at line 37 of file PciBus.c.

Definition at line 76 of file PciBus.c.

Definition at line 45 of file ComponentName.c.

Definition at line 51 of file ComponentName.c.

Definition at line 67 of file PciBus.c.

Definition at line 38 of file PciBus.c.

EFI_HANDLE gPciHostBrigeHandles[PCI_MAX_HOST_BRIDGE_NUM]

Definition at line 36 of file PciBus.c.

Definition at line 44 of file PciBus.c.

Definition at line 43 of file PciBus.c.

Definition at line 20 of file PciResourceSupport.c.

Definition at line 21 of file PciResourceSupport.c.

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