EDK2 doxygen online documents - Firmware Encoding Index 1
EDK2 doxygen online documents - Firmware Encoding Index

BeagleBoardPkg/Include/BeagleBoard.h

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00001 
00016 #ifndef __BEAGLEBOARD_PLATFORM_H__
00017 #define __BEAGLEBOARD_PLATFORM_H__
00018 
00019 // DDR attributes
00020 #define DDR_ATTRIBUTES_CACHED                ARM_MEMORY_REGION_ATTRIBUTE_WRITE_BACK
00021 #define DDR_ATTRIBUTES_UNCACHED              ARM_MEMORY_REGION_ATTRIBUTE_UNCACHED_UNBUFFERED
00022 
00023 // SoC registers. L3 interconnects
00024 #define SOC_REGISTERS_L3_PHYSICAL_BASE       0x68000000
00025 #define SOC_REGISTERS_L3_PHYSICAL_LENGTH     0x08000000
00026 #define SOC_REGISTERS_L3_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
00027 
00028 // SoC registers. L4 interconnects
00029 #define SOC_REGISTERS_L4_PHYSICAL_BASE       0x48000000
00030 #define SOC_REGISTERS_L4_PHYSICAL_LENGTH     0x08000000
00031 #define SOC_REGISTERS_L4_ATTRIBUTES          ARM_MEMORY_REGION_ATTRIBUTE_DEVICE
00032 
00033 
00034 #if 0
00035 /*******************************************
00036 // Platform Memory Map
00037 *******************************************/
00038 
00039 // Can be NOR, DOC, DRAM, SRAM
00040 #define ARM_EB_REMAP_BASE                     0x00000000
00041 #define ARM_EB_REMAP_SZ                       0x04000000
00042 
00043 // Motherboard Peripheral and On-chip peripheral
00044 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_BASE     0x10000000
00045 #define ARM_EB_SMB_MB_ON_CHIP_PERIPH_SZ       0x00100000
00046 #define ARM_EB_BOARD_PERIPH_BASE              0x10000000
00047 //#define ARM_EB_CHIP_PERIPH_BASE             0x10020000
00048 
00049 // SMC
00050 #define ARM_EB_SMC_BASE                       0x40000000
00051 #define ARM_EB_SMC_SZ                         0x20000000
00052 
00053 // NOR Flash 1
00054 #define ARM_EB_SMB_NOR_BASE                   0x40000000
00055 #define ARM_EB_SMB_NOR_SZ                     0x04000000 /* 64 MB */
00056 // DOC Flash
00057 #define ARM_EB_SMB_DOC_BASE                   0x44000000
00058 #define ARM_EB_SMB_DOC_SZ                     0x04000000 /* 64 MB */
00059 // SRAM
00060 #define ARM_EB_SMB_SRAM_BASE                  0x48000000
00061 #define ARM_EB_SMB_SRAM_SZ                    0x02000000 /* 32 MB */
00062 // USB, Ethernet, VRAM
00063 #define ARM_EB_SMB_PERIPH_BASE                0x4E000000
00064 //#define ARM_EB_SMB_PERIPH_VRAM              0x4C000000
00065 #define ARM_EB_SMB_PERIPH_SZ                  0x02000000 /* 32 MB */
00066 
00067 // DRAM
00068 #define ARM_EB_DRAM_BASE                      0x70000000
00069 #define ARM_EB_DRAM_SZ                        0x10000000
00070 
00071 // Logic Tile
00072 #define ARM_EB_LOGIC_TILE_BASE                0xC0000000
00073 #define ARM_EB_LOGIC_TILE_SZ                  0x40000000
00074 
00075 /*******************************************
00076 // Motherboard peripherals
00077 *******************************************/
00078 
00079 // Define MotherBoard SYS flags offsets (from ARM_EB_BOARD_PERIPH_BASE)
00080 #define ARM_EB_SYS_FLAGS_REG                  (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
00081 #define ARM_EB_SYS_FLAGS_SET_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00030)
00082 #define ARM_EB_SYS_FLAGS_CLR_REG              (ARM_EB_BOARD_PERIPH_BASE + 0x00034)
00083 #define ARM_EB_SYS_FLAGS_NV_REG               (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
00084 #define ARM_EB_SYS_FLAGS_NV_SET_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x00038)
00085 #define ARM_EB_SYS_FLAGS_NV_CLR_REG           (ARM_EB_BOARD_PERIPH_BASE + 0x0003C)
00086 #define ARM_EB_SYS_CLCD                       (ARM_EB_BOARD_PERIPH_BASE + 0x00050)
00087 #define ARM_EB_SYS_PROCID0_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00084)
00088 #define ARM_EB_SYS_PROCID1_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x00088)
00089 #define ARM_EB_SYS_CFGDATA_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A0)
00090 #define ARM_EB_SYS_CFGCTRL_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A4)
00091 #define ARM_EB_SYS_CFGSTAT_REG                (ARM_EB_BOARD_PERIPH_BASE + 0x000A8)
00092 
00093 // SP810 Controller
00094 #define SP810_CTRL_BASE                       (ARM_EB_BOARD_PERIPH_BASE + 0x01000)
00095 
00096 // SYSTRCL Register
00097 #define ARM_EB_SYSCTRL                                                                                    0x10001000
00098 
00099 // Uart0
00100 #define PL011_CONSOLE_UART_BASE               (ARM_EB_BOARD_PERIPH_BASE + 0x09000)
00101 #define PL011_CONSOLE_UART_SPEED              115200
00102 
00103 // SP804 Timer Bases
00104 #define SP804_TIMER0_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11000)
00105 #define SP804_TIMER1_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x11020)
00106 #define SP804_TIMER2_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12000)
00107 #define SP804_TIMER3_BASE                     (ARM_EB_BOARD_PERIPH_BASE + 0x12020)
00108 
00109 // PL301 RTC
00110 #define PL031_RTC_BASE                        (ARM_EB_BOARD_PERIPH_BASE + 0x17000)
00111 
00112 // Dynamic Memory Controller Base
00113 #define ARM_EB_DMC_BASE                       0x10018000
00114 
00115 // Static Memory Controller Base
00116 #define ARM_EB_SMC_CTRL_BASE                  0x10080000
00117 
00118 #define PL111_CLCD_BASE                       0x10020000
00119 //TODO: FIXME ... Reserved the memory in UEFI !!! Otherwise risk of corruption
00120 #define PL111_CLCD_VRAM_BASE                  0x78000000
00121 
00122 #define ARM_EB_SYS_OSCCLK4                    0x1000001C
00123 
00124 
00125 /*// System Configuration Controller register Base addresses
00126 //#define ARM_EB_SYS_CFG_CTRL_BASE                0x100E2000
00127 #define ARM_EB_SYS_CFGRW0_REG                   0x100E2000
00128 #define ARM_EB_SYS_CFGRW1_REG                   0x100E2004
00129 #define ARM_EB_SYS_CFGRW2_REG                   0x100E2008
00130 
00131 #define ARM_EB_CFGRW1_REMAP_NOR0                0
00132 #define ARM_EB_CFGRW1_REMAP_NOR1                (1 << 28)
00133 #define ARM_EB_CFGRW1_REMAP_EXT_AXI             (1 << 29)
00134 #define ARM_EB_CFGRW1_REMAP_DRAM                (1 << 30)
00135 
00136 // PL301 Fast AXI Base Address
00137 #define ARM_EB_FAXI_BASE                        0x100E9000
00138 
00139 // L2x0 Cache Controller Base Address
00140 //#define ARM_EB_L2x0_CTLR_BASE                   0x1E00A000*/
00141 
00142 
00143 // PL031 RTC - Other settings
00144 #define PL031_PPM_ACCURACY                      300000000
00145 
00146 /*******************************************
00147 // Interrupt Map
00148 *******************************************/
00149 
00150 // Timer Interrupts
00151 #define TIMER01_INTERRUPT_NUM                34
00152 #define TIMER23_INTERRUPT_NUM                35
00153 
00154 
00155 /*******************************************
00156 // EFI Memory Map in Permanent Memory (DRAM)
00157 *******************************************/
00158 
00159 // This region is allocated at the bottom of the DRAM. It will be used
00160 // for fixed address allocations such as Vector Table
00161 #define ARM_EB_EFI_FIX_ADDRESS_REGION_SZ        SIZE_8MB
00162 
00163 // This region is the memory declared to PEI as permanent memory for PEI
00164 // and DXE. EFI stacks and heaps will be declared in this region.
00165 #define ARM_EB_EFI_MEMORY_REGION_SZ             0x1000000
00166 #endif
00167 
00168 typedef enum {
00169   REVISION_XM,
00170   REVISION_UNKNOWN0,
00171   REVISION_UNKNOWN1,
00172   REVISION_UNKNOWN2,
00173   REVISION_UNKNOWN3,
00174   REVISION_C4,
00175   REVISION_C123,
00176   REVISION_AB,
00177 } BEAGLEBOARD_REVISION;
00178 
00179 #endif 
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