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EDK2 doxygen online documents - Firmware Encoding Index

MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h

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00001 
00016 #ifndef _EFI_XHCI_REG_H_
00017 #define _EFI_XHCI_REG_H_
00018 
00019 #define PCI_IF_XHCI                 0x30
00020 
00021 //
00022 // PCI Configuration Registers
00023 //
00024 #define XHC_BAR_INDEX               0x00
00025 
00026 #define XHC_PCI_BAR_OFFSET          0x10       // Memory Bar Register Offset
00027 #define XHC_PCI_BAR_MASK            0xFFFF     // Memory Base Address Mask
00028 
00029 #define USB_HUB_CLASS_CODE          0x09
00030 #define USB_HUB_SUBCLASS_CODE       0x00
00031 
00032 //============================================//
00033 //           XHCI register offset             //
00034 //============================================//
00035 
00036 //
00037 // Capability registers offset
00038 //
00039 #define XHC_CAPLENGTH_OFFSET               0x00 // Capability register length offset
00040 #define XHC_HCIVERSION_OFFSET              0x02 // Interface Version Number 02-03h
00041 #define XHC_HCSPARAMS1_OFFSET              0x04 // Structural Parameters 1
00042 #define XHC_HCSPARAMS2_OFFSET              0x08 // Structural Parameters 2
00043 #define XHC_HCSPARAMS3_OFFSET              0x0c // Structural Parameters 3
00044 #define XHC_HCCPARAMS_OFFSET               0x10 // Capability Parameters
00045 #define XHC_DBOFF_OFFSET                   0x14 // Doorbell Offset
00046 #define XHC_RTSOFF_OFFSET                  0x18 // Runtime Register Space Offset
00047 
00048 //
00049 // Operational registers offset
00050 //
00051 #define XHC_USBCMD_OFFSET                  0x0000 // USB Command Register Offset
00052 #define XHC_USBSTS_OFFSET                  0x0004 // USB Status Register Offset
00053 #define XHC_PAGESIZE_OFFSET                0x0008 // USB Page Size Register Offset
00054 #define XHC_DNCTRL_OFFSET                  0x0014 // Device Notification Control Register Offset
00055 #define XHC_CRCR_OFFSET                    0x0018 // Command Ring Control Register Offset
00056 #define XHC_DCBAAP_OFFSET                  0x0030 // Device Context Base Address Array Pointer Register Offset
00057 #define XHC_CONFIG_OFFSET                  0x0038 // Configure Register Offset
00058 #define XHC_PORTSC_OFFSET                  0x0400 // Port Status and Control Register Offset
00059 
00060 //
00061 // Runtime registers offset
00062 //
00063 #define XHC_MFINDEX_OFFSET                 0x00 // Microframe Index Register Offset
00064 #define XHC_IMAN_OFFSET                    0x20 // Interrupter X Management Register Offset
00065 #define XHC_IMOD_OFFSET                    0x24 // Interrupter X Moderation Register Offset
00066 #define XHC_ERSTSZ_OFFSET                  0x28 // Event Ring Segment Table Size Register Offset
00067 #define XHC_ERSTBA_OFFSET                  0x30 // Event Ring Segment Table Base Address Register Offset
00068 #define XHC_ERDP_OFFSET                    0x38 // Event Ring Dequeue Pointer Register Offset
00069 
00070 #define USBLEGSP_BIOS_SEMAPHORE            BIT16 // HC BIOS Owned Semaphore
00071 #define USBLEGSP_OS_SEMAPHORE              BIT24 // HC OS Owned Semaphore
00072 
00073 #pragma pack (1)
00074 typedef struct {
00075   UINT8                   MaxSlots;       // Number of Device Slots
00076   UINT16                  MaxIntrs:11;    // Number of Interrupters
00077   UINT16                  Rsvd:5;
00078   UINT8                   MaxPorts;       // Number of Ports
00079 } HCSPARAMS1;
00080 
00081 //
00082 // Structural Parameters 1 Register Bitmap Definition
00083 //
00084 typedef union {
00085   UINT32                  Dword;
00086   HCSPARAMS1              Data;
00087 } XHC_HCSPARAMS1;
00088 
00089 typedef struct {
00090   UINT32                  Ist:4;          // Isochronous Scheduling Threshold
00091   UINT32                  Erst:4;         // Event Ring Segment Table Max
00092   UINT32                  Rsvd:13;
00093   UINT32                  ScratchBufHi:5; // Max Scratchpad Buffers Hi
00094   UINT32                  Spr:1;          // Scratchpad Restore
00095   UINT32                  ScratchBufLo:5; // Max Scratchpad Buffers Lo
00096 } HCSPARAMS2;
00097 
00098 //
00099 // Structural Parameters 2 Register Bitmap Definition
00100 //
00101 typedef union {
00102   UINT32                  Dword;
00103   HCSPARAMS2              Data;
00104 } XHC_HCSPARAMS2;
00105 
00106 typedef struct {
00107   UINT16                  Ac64:1;        // 64-bit Addressing Capability
00108   UINT16                  Bnc:1;         // BW Negotiation Capability
00109   UINT16                  Csz:1;         // Context Size
00110   UINT16                  Ppc:1;         // Port Power Control
00111   UINT16                  Pind:1;        // Port Indicators
00112   UINT16                  Lhrc:1;        // Light HC Reset Capability
00113   UINT16                  Ltc:1;         // Latency Tolerance Messaging Capability
00114   UINT16                  Nss:1;         // No Secondary SID Support
00115   UINT16                  Pae:1;         // Parse All Event Data
00116   UINT16                  Rsvd:3;
00117   UINT16                  MaxPsaSize:4;  // Maximum Primary Stream Array Size
00118   UINT16                  ExtCapReg;     // xHCI Extended Capabilities Pointer
00119 } HCCPARAMS;
00120 
00121 //
00122 // Capability Parameters Register Bitmap Definition
00123 //
00124 typedef union {
00125   UINT32                  Dword;
00126   HCCPARAMS               Data;
00127 } XHC_HCCPARAMS;
00128 
00129 #pragma pack ()
00130 
00131 //
00132 // Register Bit Definition
00133 //
00134 #define XHC_USBCMD_RUN                     BIT0  // Run/Stop
00135 #define XHC_USBCMD_RESET                   BIT1  // Host Controller Reset
00136 #define XHC_USBCMD_INTE                    BIT2  // Interrupter Enable
00137 #define XHC_USBCMD_HSEE                    BIT3  // Host System Error Enable
00138 
00139 #define XHC_USBSTS_HALT                    BIT0  // Host Controller Halted
00140 #define XHC_USBSTS_HSE                     BIT2  // Host System Error
00141 #define XHC_USBSTS_EINT                    BIT3  // Event Interrupt
00142 #define XHC_USBSTS_PCD                     BIT4  // Port Change Detect
00143 #define XHC_USBSTS_SSS                     BIT8  // Save State Status
00144 #define XHC_USBSTS_RSS                     BIT9  // Restore State Status
00145 #define XHC_USBSTS_SRE                     BIT10 // Save/Restore Error
00146 #define XHC_USBSTS_CNR                     BIT11 // Host Controller Not Ready
00147 #define XHC_USBSTS_HCE                     BIT12 // Host Controller Error
00148 
00149 #define XHC_PAGESIZE_MASK                  0xFFFF // Page Size
00150 
00151 #define XHC_CRCR_RCS                       BIT0  // Ring Cycle State
00152 #define XHC_CRCR_CS                        BIT1  // Command Stop
00153 #define XHC_CRCR_CA                        BIT2  // Command Abort
00154 #define XHC_CRCR_CRR                       BIT3  // Command Ring Running
00155 
00156 #define XHC_CONFIG_MASK                    0xFF  // Command Ring Running
00157 
00158 #define XHC_PORTSC_CCS                     BIT0  // Current Connect Status
00159 #define XHC_PORTSC_PED                     BIT1  // Port Enabled/Disabled
00160 #define XHC_PORTSC_OCA                     BIT3  // Over-current Active
00161 #define XHC_PORTSC_RESET                   BIT4  // Port Reset
00162 #define XHC_PORTSC_PLS                     (BIT5|BIT6|BIT7|BIT8)     // Port Link State
00163 #define XHC_PORTSC_PP                      BIT9  // Port Power
00164 #define XHC_PORTSC_PS                      (BIT10|BIT11|BIT12|BIT13) // Port Speed
00165 #define XHC_PORTSC_LWS                     BIT16 // Port Link State Write Strobe
00166 #define XHC_PORTSC_CSC                     BIT17 // Connect Status Change
00167 #define XHC_PORTSC_PEC                     BIT18 // Port Enabled/Disabled Change
00168 #define XHC_PORTSC_WRC                     BIT19 // Warm Port Reset Change
00169 #define XHC_PORTSC_OCC                     BIT20 // Over-Current Change
00170 #define XHC_PORTSC_PRC                     BIT21 // Port Reset Change
00171 #define XHC_PORTSC_PLC                     BIT22 // Port Link State Change
00172 #define XHC_PORTSC_CEC                     BIT23 // Port Config Error Change
00173 #define XHC_PORTSC_CAS                     BIT24 // Cold Attach Status
00174 
00175 #define XHC_IMAN_IP                        BIT0  // Interrupt Pending
00176 #define XHC_IMAN_IE                        BIT1  // Interrupt Enable
00177 
00178 #define XHC_IMODI_MASK                     0x0000FFFF  // Interrupt Moderation Interval
00179 #define XHC_IMODC_MASK                     0xFFFF0000  // Interrupt Moderation Counter
00180 
00181 //
00182 // Structure to map the hardware port states to the
00183 // UEFI's port states.
00184 //
00185 typedef struct {
00186   UINT32                  HwState;
00187   UINT16                  UefiState;
00188 } USB_PORT_STATE_MAP;
00189 
00200 UINT8
00201 XhcReadCapReg8 (
00202   IN  USB_XHCI_INSTANCE   *Xhc,
00203   IN  UINT32              Offset
00204   );
00205 
00216 UINT32
00217 XhcReadCapReg (
00218   IN  USB_XHCI_INSTANCE   *Xhc,
00219   IN  UINT32              Offset
00220   );
00221 
00232 UINT32
00233 XhcReadOpReg (
00234   IN  USB_XHCI_INSTANCE   *Xhc,
00235   IN  UINT32              Offset
00236   );
00237 
00246 VOID
00247 XhcWriteOpReg (
00248   IN USB_XHCI_INSTANCE    *Xhc,
00249   IN UINT32               Offset,
00250   IN UINT32               Data
00251   );
00252 
00261 VOID
00262 XhcWriteOpReg16 (
00263   IN USB_XHCI_INSTANCE    *Xhc,
00264   IN UINT32               Offset,
00265   IN UINT16               Data
00266   );
00267 
00276 VOID
00277 XhcWriteOpReg64 (
00278   IN USB_XHCI_INSTANCE    *Xhc,
00279   IN UINT32               Offset,
00280   IN UINT64               Data
00281   );
00282 
00292 UINT32
00293 XhcReadRuntimeReg (
00294   IN  USB_XHCI_INSTANCE   *Xhc,
00295   IN  UINT32              Offset
00296   );
00297 
00307 UINT64
00308 XhcReadRuntimeReg64 (
00309   IN  USB_XHCI_INSTANCE   *Xhc,
00310   IN  UINT32              Offset
00311   );
00312 
00321 VOID
00322 XhcWriteRuntimeReg (
00323   IN USB_XHCI_INSTANCE    *Xhc,
00324   IN UINT32               Offset,
00325   IN UINT32               Data
00326   );
00327 
00336 VOID
00337 XhcWriteRuntimeReg64 (
00338   IN USB_XHCI_INSTANCE    *Xhc,
00339   IN UINT32               Offset,
00340   IN UINT64               Data
00341   );
00342 
00352 UINT32
00353 XhcReadDoorBellReg (
00354   IN  USB_XHCI_INSTANCE   *Xhc,
00355   IN  UINT32              Offset
00356   );
00357 
00366 VOID
00367 XhcWriteDoorBellReg (
00368   IN USB_XHCI_INSTANCE    *Xhc,
00369   IN UINT32               Offset,
00370   IN UINT32               Data
00371   );
00372 
00381 VOID
00382 XhcSetOpRegBit (
00383   IN USB_XHCI_INSTANCE    *Xhc,
00384   IN UINT32               Offset,
00385   IN UINT32               Bit
00386   );
00387 
00396 VOID
00397 XhcClearOpRegBit (
00398   IN USB_XHCI_INSTANCE    *Xhc,
00399   IN UINT32               Offset,
00400   IN UINT32               Bit
00401   );
00402 
00417 EFI_STATUS
00418 XhcWaitOpRegBit (
00419   IN USB_XHCI_INSTANCE    *Xhc,
00420   IN UINT32               Offset,
00421   IN UINT32               Bit,
00422   IN BOOLEAN              WaitToSet,
00423   IN UINT32               Timeout
00424   );
00425 
00435 UINT32
00436 XhcReadRuntimeReg (
00437   IN  USB_XHCI_INSTANCE   *Xhc,
00438   IN  UINT32              Offset
00439   );
00440 
00449 VOID
00450 XhcWriteRuntimeReg (
00451   IN USB_XHCI_INSTANCE    *Xhc,
00452   IN UINT32               Offset,
00453   IN UINT32               Data
00454   );
00455 
00464 VOID
00465 XhcSetRuntimeRegBit (
00466   IN USB_XHCI_INSTANCE    *Xhc,
00467   IN UINT32               Offset,
00468   IN UINT32               Bit
00469   );
00470 
00479 VOID
00480 XhcClearRuntimeRegBit (
00481   IN USB_XHCI_INSTANCE    *Xhc,
00482   IN UINT32               Offset,
00483   IN UINT32               Bit
00484   );
00485 
00495 BOOLEAN
00496 XhcIsHalt (
00497   IN USB_XHCI_INSTANCE    *Xhc
00498   );
00499 
00509 BOOLEAN
00510 XhcIsSysError (
00511   IN USB_XHCI_INSTANCE    *Xhc
00512   );
00513 
00524 EFI_STATUS
00525 XhcResetHC (
00526   IN USB_XHCI_INSTANCE    *Xhc,
00527   IN UINT32               Timeout
00528   );
00529 
00540 EFI_STATUS
00541 XhcHaltHC (
00542   IN USB_XHCI_INSTANCE   *Xhc,
00543   IN UINT32              Timeout
00544   );
00545 
00556 EFI_STATUS
00557 XhcRunHC (
00558   IN USB_XHCI_INSTANCE    *Xhc,
00559   IN UINT32               Timeout
00560   );
00561 
00570 UINT32
00571 XhcGetLegSupCapAddr (
00572   IN USB_XHCI_INSTANCE    *Xhc
00573   );
00574 
00575 #endif
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