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Data Structures | Defines | Functions

MdeModulePkg/Bus/Pci/XhciDxe/XhciReg.h File Reference

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Data Structures

struct  HCSPARAMS1
union  XHC_HCSPARAMS1
struct  HCSPARAMS2
union  XHC_HCSPARAMS2
struct  HCCPARAMS
union  XHC_HCCPARAMS
struct  USB_PORT_STATE_MAP

Defines

#define PCI_IF_XHCI   0x30
#define XHC_BAR_INDEX   0x00
#define XHC_PCI_BAR_OFFSET   0x10
#define XHC_PCI_BAR_MASK   0xFFFF
#define USB_HUB_CLASS_CODE   0x09
#define USB_HUB_SUBCLASS_CODE   0x00
#define XHC_CAPLENGTH_OFFSET   0x00
#define XHC_HCIVERSION_OFFSET   0x02
#define XHC_HCSPARAMS1_OFFSET   0x04
#define XHC_HCSPARAMS2_OFFSET   0x08
#define XHC_HCSPARAMS3_OFFSET   0x0c
#define XHC_HCCPARAMS_OFFSET   0x10
#define XHC_DBOFF_OFFSET   0x14
#define XHC_RTSOFF_OFFSET   0x18
#define XHC_USBCMD_OFFSET   0x0000
#define XHC_USBSTS_OFFSET   0x0004
#define XHC_PAGESIZE_OFFSET   0x0008
#define XHC_DNCTRL_OFFSET   0x0014
#define XHC_CRCR_OFFSET   0x0018
#define XHC_DCBAAP_OFFSET   0x0030
#define XHC_CONFIG_OFFSET   0x0038
#define XHC_PORTSC_OFFSET   0x0400
#define XHC_MFINDEX_OFFSET   0x00
#define XHC_IMAN_OFFSET   0x20
#define XHC_IMOD_OFFSET   0x24
#define XHC_ERSTSZ_OFFSET   0x28
#define XHC_ERSTBA_OFFSET   0x30
#define XHC_ERDP_OFFSET   0x38
#define USBLEGSP_BIOS_SEMAPHORE   BIT16
#define USBLEGSP_OS_SEMAPHORE   BIT24
#define XHC_USBCMD_RUN   BIT0
#define XHC_USBCMD_RESET   BIT1
#define XHC_USBCMD_INTE   BIT2
#define XHC_USBCMD_HSEE   BIT3
#define XHC_USBSTS_HALT   BIT0
#define XHC_USBSTS_HSE   BIT2
#define XHC_USBSTS_EINT   BIT3
#define XHC_USBSTS_PCD   BIT4
#define XHC_USBSTS_SSS   BIT8
#define XHC_USBSTS_RSS   BIT9
#define XHC_USBSTS_SRE   BIT10
#define XHC_USBSTS_CNR   BIT11
#define XHC_USBSTS_HCE   BIT12
#define XHC_PAGESIZE_MASK   0xFFFF
#define XHC_CRCR_RCS   BIT0
#define XHC_CRCR_CS   BIT1
#define XHC_CRCR_CA   BIT2
#define XHC_CRCR_CRR   BIT3
#define XHC_CONFIG_MASK   0xFF
#define XHC_PORTSC_CCS   BIT0
#define XHC_PORTSC_PED   BIT1
#define XHC_PORTSC_OCA   BIT3
#define XHC_PORTSC_RESET   BIT4
#define XHC_PORTSC_PLS   (BIT5|BIT6|BIT7|BIT8)
#define XHC_PORTSC_PP   BIT9
#define XHC_PORTSC_PS   (BIT10|BIT11|BIT12|BIT13)
#define XHC_PORTSC_LWS   BIT16
#define XHC_PORTSC_CSC   BIT17
#define XHC_PORTSC_PEC   BIT18
#define XHC_PORTSC_WRC   BIT19
#define XHC_PORTSC_OCC   BIT20
#define XHC_PORTSC_PRC   BIT21
#define XHC_PORTSC_PLC   BIT22
#define XHC_PORTSC_CEC   BIT23
#define XHC_PORTSC_CAS   BIT24
#define XHC_IMAN_IP   BIT0
#define XHC_IMAN_IE   BIT1
#define XHC_IMODI_MASK   0x0000FFFF
#define XHC_IMODC_MASK   0xFFFF0000

Functions

UINT8 XhcReadCapReg8 (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset)
UINT32 XhcReadCapReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset)
UINT32 XhcReadOpReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset)
VOID XhcWriteOpReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Data)
VOID XhcWriteOpReg16 (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT16 Data)
VOID XhcWriteOpReg64 (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT64 Data)
UINT32 XhcReadRuntimeReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset)
UINT64 XhcReadRuntimeReg64 (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset)
VOID XhcWriteRuntimeReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Data)
VOID XhcWriteRuntimeReg64 (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT64 Data)
UINT32 XhcReadDoorBellReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset)
VOID XhcWriteDoorBellReg (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Data)
VOID XhcSetOpRegBit (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Bit)
VOID XhcClearOpRegBit (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Bit)
EFI_STATUS XhcWaitOpRegBit (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Bit, IN BOOLEAN WaitToSet, IN UINT32 Timeout)
VOID XhcSetRuntimeRegBit (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Bit)
VOID XhcClearRuntimeRegBit (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Offset, IN UINT32 Bit)
BOOLEAN XhcIsHalt (IN USB_XHCI_INSTANCE *Xhc)
BOOLEAN XhcIsSysError (IN USB_XHCI_INSTANCE *Xhc)
EFI_STATUS XhcResetHC (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Timeout)
EFI_STATUS XhcHaltHC (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Timeout)
EFI_STATUS XhcRunHC (IN USB_XHCI_INSTANCE *Xhc, IN UINT32 Timeout)
UINT32 XhcGetLegSupCapAddr (IN USB_XHCI_INSTANCE *Xhc)

Detailed Description

This file contains the register definition of XHCI host controller.

Copyright (c) 2011, Intel Corporation. All rights reserved.
This program and the accompanying materials are licensed and made available under the terms and conditions of the BSD License which accompanies this distribution. The full text of the license may be found at http://opensource.org/licenses/bsd-license.php

THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.

Definition in file XhciReg.h.


Define Documentation

#define PCI_IF_XHCI   0x30

Definition at line 19 of file XhciReg.h.

#define USB_HUB_CLASS_CODE   0x09

Definition at line 29 of file XhciReg.h.

#define USB_HUB_SUBCLASS_CODE   0x00

Definition at line 30 of file XhciReg.h.

#define USBLEGSP_BIOS_SEMAPHORE   BIT16

Definition at line 70 of file XhciReg.h.

#define USBLEGSP_OS_SEMAPHORE   BIT24

Definition at line 71 of file XhciReg.h.

#define XHC_BAR_INDEX   0x00

Definition at line 24 of file XhciReg.h.

#define XHC_CAPLENGTH_OFFSET   0x00

Definition at line 39 of file XhciReg.h.

#define XHC_CONFIG_MASK   0xFF

Definition at line 156 of file XhciReg.h.

#define XHC_CONFIG_OFFSET   0x0038

Definition at line 57 of file XhciReg.h.

#define XHC_CRCR_CA   BIT2

Definition at line 153 of file XhciReg.h.

#define XHC_CRCR_CRR   BIT3

Definition at line 154 of file XhciReg.h.

#define XHC_CRCR_CS   BIT1

Definition at line 152 of file XhciReg.h.

#define XHC_CRCR_OFFSET   0x0018

Definition at line 55 of file XhciReg.h.

#define XHC_CRCR_RCS   BIT0

Definition at line 151 of file XhciReg.h.

#define XHC_DBOFF_OFFSET   0x14

Definition at line 45 of file XhciReg.h.

#define XHC_DCBAAP_OFFSET   0x0030

Definition at line 56 of file XhciReg.h.

#define XHC_DNCTRL_OFFSET   0x0014

Definition at line 54 of file XhciReg.h.

#define XHC_ERDP_OFFSET   0x38

Definition at line 68 of file XhciReg.h.

#define XHC_ERSTBA_OFFSET   0x30

Definition at line 67 of file XhciReg.h.

#define XHC_ERSTSZ_OFFSET   0x28

Definition at line 66 of file XhciReg.h.

#define XHC_HCCPARAMS_OFFSET   0x10

Definition at line 44 of file XhciReg.h.

#define XHC_HCIVERSION_OFFSET   0x02

Definition at line 40 of file XhciReg.h.

#define XHC_HCSPARAMS1_OFFSET   0x04

Definition at line 41 of file XhciReg.h.

#define XHC_HCSPARAMS2_OFFSET   0x08

Definition at line 42 of file XhciReg.h.

#define XHC_HCSPARAMS3_OFFSET   0x0c

Definition at line 43 of file XhciReg.h.

#define XHC_IMAN_IE   BIT1

Definition at line 176 of file XhciReg.h.

#define XHC_IMAN_IP   BIT0

Definition at line 175 of file XhciReg.h.

#define XHC_IMAN_OFFSET   0x20

Definition at line 64 of file XhciReg.h.

#define XHC_IMOD_OFFSET   0x24

Definition at line 65 of file XhciReg.h.

#define XHC_IMODC_MASK   0xFFFF0000

Definition at line 179 of file XhciReg.h.

#define XHC_IMODI_MASK   0x0000FFFF

Definition at line 178 of file XhciReg.h.

#define XHC_MFINDEX_OFFSET   0x00

Definition at line 63 of file XhciReg.h.

#define XHC_PAGESIZE_MASK   0xFFFF

Definition at line 149 of file XhciReg.h.

#define XHC_PAGESIZE_OFFSET   0x0008

Definition at line 53 of file XhciReg.h.

#define XHC_PCI_BAR_MASK   0xFFFF

Definition at line 27 of file XhciReg.h.

#define XHC_PCI_BAR_OFFSET   0x10

Definition at line 26 of file XhciReg.h.

#define XHC_PORTSC_CAS   BIT24

Definition at line 173 of file XhciReg.h.

#define XHC_PORTSC_CCS   BIT0

Definition at line 158 of file XhciReg.h.

#define XHC_PORTSC_CEC   BIT23

Definition at line 172 of file XhciReg.h.

#define XHC_PORTSC_CSC   BIT17

Definition at line 166 of file XhciReg.h.

#define XHC_PORTSC_LWS   BIT16

Definition at line 165 of file XhciReg.h.

#define XHC_PORTSC_OCA   BIT3

Definition at line 160 of file XhciReg.h.

#define XHC_PORTSC_OCC   BIT20

Definition at line 169 of file XhciReg.h.

#define XHC_PORTSC_OFFSET   0x0400

Definition at line 58 of file XhciReg.h.

#define XHC_PORTSC_PEC   BIT18

Definition at line 167 of file XhciReg.h.

#define XHC_PORTSC_PED   BIT1

Definition at line 159 of file XhciReg.h.

#define XHC_PORTSC_PLC   BIT22

Definition at line 171 of file XhciReg.h.

#define XHC_PORTSC_PLS   (BIT5|BIT6|BIT7|BIT8)

Definition at line 162 of file XhciReg.h.

#define XHC_PORTSC_PP   BIT9

Definition at line 163 of file XhciReg.h.

#define XHC_PORTSC_PRC   BIT21

Definition at line 170 of file XhciReg.h.

#define XHC_PORTSC_PS   (BIT10|BIT11|BIT12|BIT13)

Definition at line 164 of file XhciReg.h.

#define XHC_PORTSC_RESET   BIT4

Definition at line 161 of file XhciReg.h.

#define XHC_PORTSC_WRC   BIT19

Definition at line 168 of file XhciReg.h.

#define XHC_RTSOFF_OFFSET   0x18

Definition at line 46 of file XhciReg.h.

#define XHC_USBCMD_HSEE   BIT3

Definition at line 137 of file XhciReg.h.

#define XHC_USBCMD_INTE   BIT2

Definition at line 136 of file XhciReg.h.

#define XHC_USBCMD_OFFSET   0x0000

Definition at line 51 of file XhciReg.h.

#define XHC_USBCMD_RESET   BIT1

Definition at line 135 of file XhciReg.h.

#define XHC_USBCMD_RUN   BIT0

Definition at line 134 of file XhciReg.h.

#define XHC_USBSTS_CNR   BIT11

Definition at line 146 of file XhciReg.h.

#define XHC_USBSTS_EINT   BIT3

Definition at line 141 of file XhciReg.h.

#define XHC_USBSTS_HALT   BIT0

Definition at line 139 of file XhciReg.h.

#define XHC_USBSTS_HCE   BIT12

Definition at line 147 of file XhciReg.h.

#define XHC_USBSTS_HSE   BIT2

Definition at line 140 of file XhciReg.h.

#define XHC_USBSTS_OFFSET   0x0004

Definition at line 52 of file XhciReg.h.

#define XHC_USBSTS_PCD   BIT4

Definition at line 142 of file XhciReg.h.

#define XHC_USBSTS_RSS   BIT9

Definition at line 144 of file XhciReg.h.

#define XHC_USBSTS_SRE   BIT10

Definition at line 145 of file XhciReg.h.

#define XHC_USBSTS_SSS   BIT8

Definition at line 143 of file XhciReg.h.


Function Documentation

VOID XhcClearOpRegBit ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Bit 
)

Clear one bit of the operational register while keeping other bits.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the operational register.
BitThe bit mask of the register to clear.

Definition at line 584 of file XhciReg.c.

VOID XhcClearRuntimeRegBit ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Bit 
)

Clear one bit of the runtime register while keeping other bits.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the runtime register.
BitThe bit mask of the register to set.

Definition at line 539 of file XhciReg.c.

UINT32 XhcGetLegSupCapAddr ( IN USB_XHCI_INSTANCE Xhc)

Calculate the XHCI legacy support capability register offset.

Parameters:
XhcThe XHCI Instance.
Returns:
The offset of XHCI legacy support capability register.

Definition at line 685 of file XhciReg.c.

EFI_STATUS XhcHaltHC ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Timeout 
)

Halt the XHCI host controller.

Parameters:
XhcThe XHCI Instance.
TimeoutTime to wait before abort (in millisecond, ms).
Returns:
EFI_SUCCESS The XHCI host controller is halt.
EFI_TIMEOUT Failed to halt the XHCI before Timeout.

Definition at line 795 of file XhciReg.c.

BOOLEAN XhcIsHalt ( IN USB_XHCI_INSTANCE Xhc)

Whether the XHCI host controller is halted.

Parameters:
XhcThe XHCI Instance.
Return values:
TRUEThe controller is halted.
FALSEIt isn't halted.

Definition at line 723 of file XhciReg.c.

BOOLEAN XhcIsSysError ( IN USB_XHCI_INSTANCE Xhc)

Whether system error occurred.

Parameters:
XhcThe XHCI Instance.
Return values:
TRUESystem error happened.
FALSENo system error.

Definition at line 741 of file XhciReg.c.

UINT32 XhcReadCapReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset 
)

Read 4-bytes width XHCI capability register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 4-bytes width capability register.
Returns:
The register content read.
Return values:
Iferr, return 0xFFFFFFFF.

Definition at line 65 of file XhciReg.c.

UINT8 XhcReadCapReg8 ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset 
)

Read 1-byte width XHCI capability register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 1-byte width capability register.
Returns:
The register content read.
Return values:
Iferr, return 0xFFFF.

Read 1-byte width XHCI capability register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 1-byte width capability register.
Returns:
The register content read.
Return values:
Iferr, return 0xFF.

Definition at line 29 of file XhciReg.c.

UINT32 XhcReadDoorBellReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset 
)

Read XHCI door bell register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the door bell register.
Returns:
The register content read

Definition at line 237 of file XhciReg.c.

UINT32 XhcReadOpReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset 
)

Read 4-bytes width XHCI Operational register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 4-bytes width operational register.
Returns:
The register content read.
Return values:
Iferr, return 0xFFFFFFFF.

Definition at line 101 of file XhciReg.c.

UINT32 XhcReadRuntimeReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset 
)

Read XHCI runtime register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the runtime register.
Returns:
The register content read

Definition at line 307 of file XhciReg.c.

UINT64 XhcReadRuntimeReg64 ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset 
)

Read 8-bytes width XHCI runtime register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 8-bytes width runtime register.
Returns:
The register content read

Definition at line 344 of file XhciReg.c.

EFI_STATUS XhcResetHC ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Timeout 
)

Reset the XHCI host controller.

Parameters:
XhcThe XHCI Instance.
TimeoutTime to wait before abort (in millisecond, ms).
Return values:
EFI_SUCCESSThe XHCI host controller is reset.
Returns:
Others Failed to reset the XHCI before Timeout.

Definition at line 759 of file XhciReg.c.

EFI_STATUS XhcRunHC ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Timeout 
)

Set the XHCI host controller to run.

Parameters:
XhcThe XHCI Instance.
TimeoutTime to wait before abort (in millisecond, ms).
Returns:
EFI_SUCCESS The XHCI host controller is running.
EFI_TIMEOUT Failed to set the XHCI to run before Timeout.

Definition at line 819 of file XhciReg.c.

VOID XhcSetOpRegBit ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Bit 
)

Set one bit of the operational register while keeping other bits.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the operational register.
BitThe bit mask of the register to set.

Definition at line 561 of file XhciReg.c.

VOID XhcSetRuntimeRegBit ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Bit 
)

Set one bit of the runtime register while keeping other bits.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the runtime register.
BitThe bit mask of the register to set.

Definition at line 517 of file XhciReg.c.

EFI_STATUS XhcWaitOpRegBit ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Bit,
IN BOOLEAN  WaitToSet,
IN UINT32  Timeout 
)

Wait the operation register's bit as specified by Bit to be set (or clear).

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the operational register.
BitThe bit of the register to wait for.
WaitToSetWait the bit to set or clear.
TimeoutThe time to wait before abort (in millisecond, ms).
Return values:
EFI_SUCCESSThe bit successfully changed by host controller.
EFI_TIMEOUTThe time out occurred.

Wait the operation register's bit as specified by Bit to become set (or clear).

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the operation register.
BitThe bit of the register to wait for.
WaitToSetWait the bit to set or clear.
TimeoutThe time to wait before abort (in millisecond, ms).
Return values:
EFI_SUCCESSThe bit successfully changed by host controller.
EFI_TIMEOUTThe time out occurred.

Definition at line 612 of file XhciReg.c.

VOID XhcWriteDoorBellReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Data 
)

Write the data to the XHCI door bell register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the door bell register.
DataThe data to write.

Definition at line 273 of file XhciReg.c.

VOID XhcWriteOpReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Data 
)

Write the data to the 4-bytes width XHCI operational register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 4-bytes width operational register.
DataThe data to write.

Definition at line 137 of file XhciReg.c.

VOID XhcWriteOpReg16 ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT16  Data 
)

Write the data to the 2-bytes width XHCI operational register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 2-bytes width operational register.
DataThe data to write.

Definition at line 170 of file XhciReg.c.

VOID XhcWriteOpReg64 ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT64  Data 
)

Write the data to the 8-bytes width XHCI operational register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 8-bytes width operational register.
DataThe data to write.

Definition at line 203 of file XhciReg.c.

VOID XhcWriteRuntimeReg ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT32  Data 
)

Write the data to the XHCI runtime register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the runtime register.
DataThe data to write.

Definition at line 380 of file XhciReg.c.

VOID XhcWriteRuntimeReg64 ( IN USB_XHCI_INSTANCE Xhc,
IN UINT32  Offset,
IN UINT64  Data 
)

Write the data to the 8-bytes width XHCI runtime register.

Parameters:
XhcThe XHCI Instance.
OffsetThe offset of the 8-bytes width runtime register.
DataThe data to write.

Definition at line 413 of file XhciReg.c.

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