EDK2 doxygen online documents - Firmware Encoding Index 1
EDK2 doxygen online documents - Firmware Encoding Index

EdkCompatibilityPkg/Foundation/Library/EdkIIGlueLib/Library/BasePciCf8Lib/PciLib.c

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00001 /*++
00002 
00003 Copyright (c) 2004 - 2006, Intel Corporation. All rights reserved.<BR>
00004 This program and the accompanying materials                          
00005 are licensed and made available under the terms and conditions of the BSD License         
00006 which accompanies this distribution.  The full text of the license may be found at        
00007 http://opensource.org/licenses/bsd-license.php                                            
00008                                                                                           
00009 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,                     
00010 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.  
00011 
00012 Module Name:
00013 
00014   PciLib.c
00015   
00016 Abstract: 
00017 
00018   PCI Library.
00019 
00020 --*/
00021 
00022 #include "EdkIIGlueBase.h"
00023 
00024 //
00025 // Declare I/O Ports used to perform PCI Confguration Cycles
00026 //
00027 #define PCI_CONFIGURATION_ADDRESS_PORT  0xCF8
00028 #define PCI_CONFIGURATION_DATA_PORT     0xCFC
00029 
00030 //
00031 // Declare macro to convert PCI Library formatted address to CF8 formatted address
00032 //
00033 // PCI Library formatted address    CF8 Formatted Address
00034 // =============================    ======================
00035 //    Bits 00..11  Register           Bits 00..07  Register
00036 //    Bits 12..14  Function           Bits 08..10  Function
00037 //    Bits 15..19  Device             Bits 11..15  Device
00038 //    Bits 20..27  Bus                Bits 16..23  Bus
00039 //    Bits 28..31  Reserved(MBZ)      Bits 24..30  Reserved(MBZ)
00040 //                                    Bits 31..31  Must be 1
00041 //
00042 
00051 #define ASSERT_INVALID_PCI_ADDRESS(A,M) \
00052   ASSERT (((A) & (~0xffff0ff | (M))) == 0)
00053 
00062 #define PCI_TO_CF8_ADDRESS(A) \
00063   ((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))
00064 
00081 UINT8
00082 EFIAPI
00083 PciCf8Read8 (
00084   IN      UINTN                     Address
00085   )
00086 {
00087   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00088   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00089   return IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));
00090 }
00091 
00109 UINT8
00110 EFIAPI
00111 PciCf8Write8 (
00112   IN      UINTN                     Address,
00113   IN      UINT8                     Value
00114   )
00115 {
00116   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00117   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00118   return IoWrite8 (
00119            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00120            Value
00121            );
00122 }
00123 
00145 UINT8
00146 EFIAPI
00147 PciCf8Or8 (
00148   IN      UINTN                     Address,
00149   IN      UINT8                     OrData
00150   )
00151 {
00152   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00153   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00154   return IoOr8 (
00155            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00156            OrData
00157            );
00158 }
00159 
00181 UINT8
00182 EFIAPI
00183 PciCf8And8 (
00184   IN      UINTN                     Address,
00185   IN      UINT8                     AndData
00186   )
00187 {
00188   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00189   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00190   return IoAnd8 (
00191            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00192            AndData
00193            );
00194 }
00195 
00219 UINT8
00220 EFIAPI
00221 PciCf8AndThenOr8 (
00222   IN      UINTN                     Address,
00223   IN      UINT8                     AndData,
00224   IN      UINT8                     OrData
00225   )
00226 {
00227   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00228   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00229   return IoAndThenOr8 (
00230            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00231            AndData,
00232            OrData
00233            );
00234 }
00235 
00258 UINT8
00259 EFIAPI
00260 PciCf8BitFieldRead8 (
00261   IN      UINTN                     Address,
00262   IN      UINTN                     StartBit,
00263   IN      UINTN                     EndBit
00264   )
00265 {
00266   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00267   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00268   return IoBitFieldRead8 (
00269            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00270            StartBit,
00271            EndBit
00272            );
00273 }
00274 
00299 UINT8
00300 EFIAPI
00301 PciCf8BitFieldWrite8 (
00302   IN      UINTN                     Address,
00303   IN      UINTN                     StartBit,
00304   IN      UINTN                     EndBit,
00305   IN      UINT8                     Value
00306   )
00307 {
00308   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00309   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00310   return IoBitFieldWrite8 (
00311            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00312            StartBit,
00313            EndBit,
00314            Value
00315            );
00316 }
00317 
00345 UINT8
00346 EFIAPI
00347 PciCf8BitFieldOr8 (
00348   IN      UINTN                     Address,
00349   IN      UINTN                     StartBit,
00350   IN      UINTN                     EndBit,
00351   IN      UINT8                     OrData
00352   )
00353 {
00354   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00355   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00356   return IoBitFieldOr8 (
00357            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00358            StartBit,
00359            EndBit,
00360            OrData
00361            );
00362 }
00363 
00391 UINT8
00392 EFIAPI
00393 PciCf8BitFieldAnd8 (
00394   IN      UINTN                     Address,
00395   IN      UINTN                     StartBit,
00396   IN      UINTN                     EndBit,
00397   IN      UINT8                     AndData
00398   )
00399 {
00400   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00401   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00402   return IoBitFieldAnd8 (
00403            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00404            StartBit,
00405            EndBit,
00406            AndData
00407            );
00408 }
00409 
00440 UINT8
00441 EFIAPI
00442 PciCf8BitFieldAndThenOr8(
00443   IN      UINTN                     Address,
00444   IN      UINTN                     StartBit,
00445   IN      UINTN                     EndBit,
00446   IN      UINT8                     AndData,
00447   IN      UINT8                     OrData
00448   )
00449 {
00450   ASSERT_INVALID_PCI_ADDRESS (Address, 0);
00451   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00452   return IoBitFieldAndThenOr8 (
00453            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),
00454            StartBit,
00455            EndBit,
00456            AndData,
00457            OrData
00458            );
00459 }
00460 
00478 UINT16
00479 EFIAPI
00480 PciCf8Read16 (
00481   IN      UINTN                     Address
00482   )
00483 {
00484   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00485   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00486   return IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));
00487 }
00488 
00507 UINT16
00508 EFIAPI
00509 PciCf8Write16 (
00510   IN      UINTN                     Address,
00511   IN      UINT16                    Value
00512   )
00513 {
00514   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00515   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00516   return IoWrite16 (
00517            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00518            Value
00519            );
00520 }
00521 
00544 UINT16
00545 EFIAPI
00546 PciCf8Or16 (
00547   IN      UINTN                     Address,
00548   IN      UINT16                    OrData
00549   )
00550 {
00551   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00552   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00553   return IoOr16 (
00554            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00555            OrData
00556            );
00557 }
00558 
00581 UINT16
00582 EFIAPI
00583 PciCf8And16 (
00584   IN      UINTN                     Address,
00585   IN      UINT16                    AndData
00586   )
00587 {
00588   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00589   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00590   return IoAnd16 (
00591            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00592            AndData
00593            );
00594 }
00595 
00620 UINT16
00621 EFIAPI
00622 PciCf8AndThenOr16 (
00623   IN      UINTN                     Address,
00624   IN      UINT16                    AndData,
00625   IN      UINT16                    OrData
00626   )
00627 {
00628   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00629   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00630   return IoAndThenOr16 (
00631            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00632            AndData,
00633            OrData
00634            );
00635 }
00636 
00660 UINT16
00661 EFIAPI
00662 PciCf8BitFieldRead16 (
00663   IN      UINTN                     Address,
00664   IN      UINTN                     StartBit,
00665   IN      UINTN                     EndBit
00666   )
00667 {
00668   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00669   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00670   return IoBitFieldRead16 (
00671            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00672            StartBit,
00673            EndBit
00674            );
00675 }
00676 
00702 UINT16
00703 EFIAPI
00704 PciCf8BitFieldWrite16 (
00705   IN      UINTN                     Address,
00706   IN      UINTN                     StartBit,
00707   IN      UINTN                     EndBit,
00708   IN      UINT16                    Value
00709   )
00710 {
00711   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00712   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00713   return IoBitFieldWrite16 (
00714            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00715            StartBit,
00716            EndBit,
00717            Value
00718            );
00719 }
00720 
00749 UINT16
00750 EFIAPI
00751 PciCf8BitFieldOr16 (
00752   IN      UINTN                     Address,
00753   IN      UINTN                     StartBit,
00754   IN      UINTN                     EndBit,
00755   IN      UINT16                    OrData
00756   )
00757 {
00758   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00759   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00760   return IoBitFieldOr16 (
00761            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00762            StartBit,
00763            EndBit,
00764            OrData
00765            );
00766 }
00767 
00796 UINT16
00797 EFIAPI
00798 PciCf8BitFieldAnd16 (
00799   IN      UINTN                     Address,
00800   IN      UINTN                     StartBit,
00801   IN      UINTN                     EndBit,
00802   IN      UINT16                    AndData
00803   )
00804 {
00805   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00806   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00807   return IoBitFieldAnd16 (
00808            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00809            StartBit,
00810            EndBit,
00811            AndData
00812            );
00813 }
00814 
00846 UINT16
00847 EFIAPI
00848 PciCf8BitFieldAndThenOr16(
00849   IN      UINTN                     Address,
00850   IN      UINTN                     StartBit,
00851   IN      UINTN                     EndBit,
00852   IN      UINT16                    AndData,
00853   IN      UINT16                    OrData
00854   )
00855 {
00856   ASSERT_INVALID_PCI_ADDRESS (Address, 1);
00857   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00858   return IoBitFieldAndThenOr16 (
00859            PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),
00860            StartBit,
00861            EndBit,
00862            AndData,
00863            OrData
00864            );
00865 }
00866 
00884 UINT32
00885 EFIAPI
00886 PciCf8Read32 (
00887   IN      UINTN                     Address
00888   )
00889 {
00890   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
00891   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00892   return IoRead32 (PCI_CONFIGURATION_DATA_PORT);
00893 }
00894 
00913 UINT32
00914 EFIAPI
00915 PciCf8Write32 (
00916   IN      UINTN                     Address,
00917   IN      UINT32                    Value
00918   )
00919 {
00920   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
00921   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00922   return IoWrite32 (
00923            PCI_CONFIGURATION_DATA_PORT,
00924            Value
00925            );
00926 }
00927 
00950 UINT32
00951 EFIAPI
00952 PciCf8Or32 (
00953   IN      UINTN                     Address,
00954   IN      UINT32                    OrData
00955   )
00956 {
00957   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
00958   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00959   return IoOr32 (
00960            PCI_CONFIGURATION_DATA_PORT,
00961            OrData
00962            );
00963 }
00964 
00987 UINT32
00988 EFIAPI
00989 PciCf8And32 (
00990   IN      UINTN                     Address,
00991   IN      UINT32                    AndData
00992   )
00993 {
00994   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
00995   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
00996   return IoAnd32 (
00997            PCI_CONFIGURATION_DATA_PORT,
00998            AndData
00999            );
01000 }
01001 
01026 UINT32
01027 EFIAPI
01028 PciCf8AndThenOr32 (
01029   IN      UINTN                     Address,
01030   IN      UINT32                    AndData,
01031   IN      UINT32                    OrData
01032   )
01033 {
01034   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
01035   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
01036   return IoAndThenOr32 (
01037            PCI_CONFIGURATION_DATA_PORT,
01038            AndData,
01039            OrData
01040            );
01041 }
01042 
01066 UINT32
01067 EFIAPI
01068 PciCf8BitFieldRead32 (
01069   IN      UINTN                     Address,
01070   IN      UINTN                     StartBit,
01071   IN      UINTN                     EndBit
01072   )
01073 {
01074   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
01075   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
01076   return IoBitFieldRead32 (
01077            PCI_CONFIGURATION_DATA_PORT,
01078            StartBit,
01079            EndBit
01080            );
01081 }
01082 
01108 UINT32
01109 EFIAPI
01110 PciCf8BitFieldWrite32 (
01111   IN      UINTN                     Address,
01112   IN      UINTN                     StartBit,
01113   IN      UINTN                     EndBit,
01114   IN      UINT32                    Value
01115   )
01116 {
01117   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
01118   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
01119   return IoBitFieldWrite32 (
01120            PCI_CONFIGURATION_DATA_PORT,
01121            StartBit,
01122            EndBit,
01123            Value
01124            );
01125 }
01126 
01155 UINT32
01156 EFIAPI
01157 PciCf8BitFieldOr32 (
01158   IN      UINTN                     Address,
01159   IN      UINTN                     StartBit,
01160   IN      UINTN                     EndBit,
01161   IN      UINT32                    OrData
01162   )
01163 {
01164   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
01165   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
01166   return IoBitFieldOr32 (
01167            PCI_CONFIGURATION_DATA_PORT,
01168            StartBit,
01169            EndBit,
01170            OrData
01171            );
01172 }
01173 
01202 UINT32
01203 EFIAPI
01204 PciCf8BitFieldAnd32 (
01205   IN      UINTN                     Address,
01206   IN      UINTN                     StartBit,
01207   IN      UINTN                     EndBit,
01208   IN      UINT32                    AndData
01209   )
01210 {
01211   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
01212   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
01213   return IoBitFieldAnd32 (
01214            PCI_CONFIGURATION_DATA_PORT,
01215            StartBit,
01216            EndBit,
01217            AndData
01218            );
01219 }
01220 
01252 UINT32
01253 EFIAPI
01254 PciCf8BitFieldAndThenOr32(
01255   IN      UINTN                     Address,
01256   IN      UINTN                     StartBit,
01257   IN      UINTN                     EndBit,
01258   IN      UINT32                    AndData,
01259   IN      UINT32                    OrData
01260   )
01261 {
01262   ASSERT_INVALID_PCI_ADDRESS (Address, 3);
01263   IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));
01264   return IoBitFieldAndThenOr32 (
01265            PCI_CONFIGURATION_DATA_PORT,
01266            StartBit,
01267            EndBit,
01268            AndData,
01269            OrData
01270            );
01271 }
01272 
01297 UINTN
01298 EFIAPI
01299 PciCf8ReadBuffer (
01300   IN      UINTN                     StartAddress,
01301   IN      UINTN                     Size,
01302   OUT     VOID                      *Buffer
01303   )
01304 {
01305   UINTN                             ReturnValue;
01306 
01307   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
01308   ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
01309 
01310   if (Size == 0) {
01311     return Size;
01312   }
01313 
01314   ASSERT (Buffer != NULL);
01315 
01316   //
01317   // Save Size for return
01318   //
01319   ReturnValue = Size;
01320 
01321   if ((StartAddress & 1) != 0) {
01322     //
01323     // Read a byte if StartAddress is byte aligned
01324     //
01325     *(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);
01326     StartAddress += sizeof (UINT8);
01327     Size -= sizeof (UINT8);
01328     Buffer = (UINT8*)Buffer + 1;
01329   }
01330 
01331   if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
01332     //
01333     // Read a word if StartAddress is word aligned
01334     //
01335     *(volatile UINT16 *)Buffer = PciCf8Read16 (StartAddress);
01336     StartAddress += sizeof (UINT16);
01337     Size -= sizeof (UINT16);
01338     Buffer = (UINT16*)Buffer + 1;
01339   }
01340 
01341   while (Size >= sizeof (UINT32)) {
01342     //
01343     // Read as many double words as possible
01344     //
01345     *(volatile UINT32 *)Buffer = PciCf8Read32 (StartAddress);
01346     StartAddress += sizeof (UINT32);
01347     Size -= sizeof (UINT32);
01348     Buffer = (UINT32*)Buffer + 1;
01349   }
01350 
01351   if (Size >= sizeof (UINT16)) {
01352     //
01353     // Read the last remaining word if exist
01354     //
01355     *(volatile UINT16 *)Buffer = PciCf8Read16 (StartAddress);
01356     StartAddress += sizeof (UINT16);
01357     Size -= sizeof (UINT16);
01358     Buffer = (UINT16*)Buffer + 1;
01359   }
01360 
01361   if (Size >= sizeof (UINT8)) {
01362     //
01363     // Read the last remaining byte if exist
01364     //
01365     *(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);
01366   }
01367 
01368   return ReturnValue;
01369 }
01370 
01396 UINTN
01397 EFIAPI
01398 PciCf8WriteBuffer (
01399   IN      UINTN                     StartAddress,
01400   IN      UINTN                     Size,
01401   IN      VOID                      *Buffer
01402   )
01403 {
01404   UINTN                             ReturnValue;
01405 
01406   ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);
01407   ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);
01408 
01409   if (Size == 0) {
01410     return 0;
01411   }
01412 
01413   ASSERT (Buffer != NULL);
01414 
01415   //
01416   // Save Size for return
01417   //
01418   ReturnValue = Size;
01419 
01420   if ((StartAddress & 1) != 0) {
01421     //
01422     // Write a byte if StartAddress is byte aligned
01423     //
01424     PciCf8Write8 (StartAddress, *(UINT8*)Buffer);
01425     StartAddress += sizeof (UINT8);
01426     Size -= sizeof (UINT8);
01427     Buffer = (UINT8*)Buffer + 1;
01428   }
01429 
01430   if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {
01431     //
01432     // Write a word if StartAddress is word aligned
01433     //
01434     PciCf8Write16 (StartAddress, *(UINT16*)Buffer);
01435     StartAddress += sizeof (UINT16);
01436     Size -= sizeof (UINT16);
01437     Buffer = (UINT16*)Buffer + 1;
01438   }
01439 
01440   while (Size >= sizeof (UINT32)) {
01441     //
01442     // Write as many double words as possible
01443     //
01444     PciCf8Write32 (StartAddress, *(UINT32*)Buffer);
01445     StartAddress += sizeof (UINT32);
01446     Size -= sizeof (UINT32);
01447     Buffer = (UINT32*)Buffer + 1;
01448   }
01449 
01450   if (Size >= sizeof (UINT16)) {
01451     //
01452     // Write the last remaining word if exist
01453     //
01454     PciCf8Write16 (StartAddress, *(UINT16*)Buffer);
01455     StartAddress += sizeof (UINT16);
01456     Size -= sizeof (UINT16);
01457     Buffer = (UINT16*)Buffer + 1;
01458   }
01459 
01460   if (Size >= sizeof (UINT8)) {
01461     //
01462     // Write the last remaining byte if exist
01463     //
01464     PciCf8Write8 (StartAddress, *(UINT8*)Buffer);
01465   }
01466 
01467   return ReturnValue;
01468 }
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