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EDK2 doxygen online documents - Firmware Encoding Index

S3C24xxPkg/Sec/include/s3c2440.h

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00001 /*
00002  * vivi/include/s3c2440.h
00003  *
00004  * Definition of constants related to the S3C2410 microprocessor(based on ARM 290T).
00005  * This file is based on the S3C2400 User Manual 2002,01,23.
00006  *
00007  * Copyright (C) 2002 MIZI Research, Inc.
00008  *
00009  *  Author: Janghoon Lyu <nandy@mizi.com>
00010  *  Date  : $Date: 2004/02/04 06:22:25 $
00011  *
00012  *  $Revision: 1.1.1.1 $
00013  */
00014 
00015 /*
00016  * History
00017  * 
00018  * 2002-05-14: Janghoon Lyu <nandy@mizi.com>
00019  *    - Initial code
00020  */
00021 
00022 #include "hardware.h"
00023 #include "bitfield.h"
00024 
00025 #define USR26_MODE              0x00
00026 #define FIQ26_MODE              0x01
00027 #define IRQ26_MODE              0x02
00028 #define SVC26_MODE              0x03
00029 #define USR_MODE                0x10
00030 #define FIQ_MODE                0x11
00031 #define IRQ_MODE                0x12
00032 #define SVC_MODE                0x13
00033 #define ABT_MODE                0x17
00034 #define UND_MODE                0x1b
00035 #define SYSTEM_MODE             0x1f
00036 #define MODE_MASK               0x1f
00037 #define F_BIT                   0x40
00038 #define I_BIT                   0x80
00039 #define CC_V_BIT                (1 << 28)
00040 #define CC_C_BIT                (1 << 29)
00041 #define CC_Z_BIT                (1 << 30)
00042 #define CC_N_BIT                (1 << 31)
00043 
00044 /* Register 1. Control Register */
00045 #define R1_nF                   (1 << 30)
00046 #define R1_iA                   (1 << 31)
00047 
00048 
00049 /* Memory Controller */
00050 #define MEM_CTL_BASE            0x48000000
00051 #define bMEMCTL(Nb)             __REGl(MEM_CTL_BASE + (Nb))
00052 /* Offset */
00053 #define oBWSCON                 0x00    /* R/W, Bus width and wait status ctrl reg. */
00054 #define oBANKCON0               0x04    /* R/W, Bank 0 control reg. */
00055 #define oBANKCON1               0x08    /* R/W, Bank 1 control reg. */
00056 #define oBANKCON2               0x0C    /* R/W, Bank 2 control reg. */
00057 #define oBANKCON3               0x10    /* R/W, Bank 3 control reg. */
00058 #define oBANKCON4               0x14    /* R/W, Bank 4 control reg. */
00059 #define oBANKCON5               0x18    /* R/W, Bank 5 control reg. */
00060 #define oBANKCON6               0x1C    /* R/W, Bank 6 control reg. */
00061 #define oBANKCON7               0x20    /* R/W, Bank 7 control reg. */
00062 #define oREFRESH                0x24    /* R/W, SDRAM refresh control register */
00063 #define oBANKSIZE               0x28    /* R/W, Flexible bank size register */
00064 #define oMRSRB6                 0x2C    /* R/W, Mode register set register bank 6 */
00065 #define oMRSRB7                 0x2C    /* R/W, Mode register set register bank 7 */
00066 /* Registers */
00067 #define BWSCON                  bMEMCTL(oBWSCON)
00068 #define BANKCON0                bMEMCTL(oBANKCON0)
00069 #define BANKCON1                bMEMCTL(oBANKCON1)
00070 #define BANKCON2                bMEMCTL(oBANKCON2)
00071 #define BANKCON3                bMEMCTL(oBANKCON3)
00072 #define BANKCON4                bMEMCTL(oBANKCON4)
00073 #define BANKCON5                bMEMCTL(oBANKCON5)
00074 #define BANKCON6                bMEMCTL(oBANKCON6)
00075 #define BANKCON7                bMEMCTL(oBANKCON7)
00076 #define REFRESH                 bMEMCTL(oREFRESH)
00077 #define BANKSIZE                bMEMCTL(oBANKSIZE)
00078 #define MRSRB6                  bMEMCTL(oMRSRB6)
00079 #define MRSRB7                  bMEMCTL(oMRSRB7)
00080 /* Bits */
00081 #define SELF_REFRESH            (1 << 22)
00082 
00083 /* Clock and Power Management */
00084 #define CLK_CTL_BASE            0x4C000000
00085 #define bCLKCTL(Nb)             __REGl(CLK_CTL_BASE + (Nb))
00086 /* Offset */
00087 #define oLOCKTIME               0x00    /* R/W, PLL lock time count register */
00088 #define oMPLLCON                0x04    /* R/W, MPLL configuration register */
00089 #define oUPLLCON                0x08    /* R/W, UPLL configuration register */
00090 #define oCLKCON                 0x0C    /* R/W, Clock generator control reg. */
00091 #define oCLKSLOW                0x10    /* R/W, Slow clock control register */
00092 #define oCLKDIVN                0x14    /* R/W, Clock divider control */
00093 /* Registers */
00094 #define LOCKTIME                bCLKCTL(oLOCKTIME)
00095 #define MPLLCON                 bCLKCTL(oMPLLCON)
00096 #define UPLLCON                 bCLKCTL(oUPLLCON)
00097 #define CLKCON                  bCLKCTL(oCLKCON)
00098 #define CLKSLOW                 bCLKCTL(oCLKSLOW)
00099 #define CLKDIVN                 bCLKCTL(oCLKDIVN)
00100 /* Fields */
00101 #define fMPLL_MDIV              Fld(8,12)
00102 #define fMPLL_PDIV              Fld(6,4)
00103 #define fMPLL_SDIV              Fld(2,0)
00104 /* macros */
00105 #define GET_MDIV(x)             FExtr(x, fMPLL_MDIV)
00106 #define GET_PDIV(x)             FExtr(x, fMPLL_PDIV)
00107 #define GET_SDIV(x)             FExtr(x, fMPLL_SDIV)
00108 
00109 /* GPIO */
00110 #define GPIO_CTL_BASE           0x56000000
00111 #define bGPIO(p,o)              __REGl(GPIO_CTL_BASE + (p) + (o))
00112 /* Offset */
00113 #define oGPIO_CON               0x0     /* R/W, Configures the pins of the port */
00114 #define oGPIO_DAT               0x4     /* R/W, Data register for port */
00115 #define oGPIO_UP                0x8     /* R/W, Pull-up disable register */
00116 #define oGPIO_RESERVED          0xC     /* R/W, Reserved */
00117 #define oGPIO_A                 0x00
00118 #define oGPIO_B                 0x10
00119 #define oGPIO_C                 0x20
00120 #define oGPIO_D                 0x30
00121 #define oGPIO_E                 0x40
00122 #define oGPIO_F                 0x50
00123 #define oGPIO_G                 0x60
00124 #define oGPIO_H                 0x70
00125 #define oMISCCR                 0x80    /* R/W, Miscellaneous control register */
00126 #define oDCLKCON                0x84    /* R/W, DCLK0/1 control register */
00127 #define oEXTINT0                0x88    /* R/W, External interrupt control reg. 0 */
00128 #define oEXTINT1                0x8C    /* R/W, External interrupt control reg. 1 */
00129 #define oEXTINT2                0x90    /* R/W, External interrupt control reg. 2 */
00130 #define oEINTFLT0               0x94    /* R/W, Reserved */
00131 #define oEINTFLT1               0x98    /* R/W, Reserved */
00132 #define oEINTFLT2               0x9C    /* R/W, External interrupt control reg. 2 */
00133 #define oEINTFLT3               0xA0    /* R/W, External interrupt control reg. 3 */
00134 #define oEINTMASK               0xA4    /* R/W, External interrupt mask register */
00135 #define oEINTPEND               0xA8    /* R/W, External interrupt pending reg. */
00136 /* Registers */
00137 #define GPACON                  bGPIO(oGPIO_A, oGPIO_CON)
00138 #define GPADAT                  bGPIO(oGPIO_A, oGPIO_DAT)
00139 #define GPBCON                  bGPIO(oGPIO_B, oGPIO_CON)
00140 #define GPBDAT                  bGPIO(oGPIO_B, oGPIO_DAT)
00141 #define GPBUP                   bGPIO(oGPIO_B, oGPIO_UP)
00142 #define GPCCON                  bGPIO(oGPIO_C, oGPIO_CON)
00143 #define GPCDAT                  bGPIO(oGPIO_C, oGPIO_DAT)
00144 #define GPCUP                   bGPIO(oGPIO_C, oGPIO_UP)
00145 #define GPDCON                  bGPIO(oGPIO_D, oGPIO_CON)
00146 #define GPDDAT                  bGPIO(oGPIO_D, oGPIO_DAT)
00147 #define GPDUP                   bGPIO(oGPIO_D, oGPIO_UP)
00148 #define GPECON                  bGPIO(oGPIO_E, oGPIO_CON)
00149 #define GPEDAT                  bGPIO(oGPIO_E, oGPIO_DAT)
00150 #define GPEUP                   bGPIO(oGPIO_E, oGPIO_UP)
00151 #define GPFCON                  bGPIO(oGPIO_F, oGPIO_CON)
00152 #define GPFDAT                  bGPIO(oGPIO_F, oGPIO_DAT)
00153 #define GPFUP                   bGPIO(oGPIO_F, oGPIO_UP)
00154 #define GPGCON                  bGPIO(oGPIO_G, oGPIO_CON)
00155 #define GPGDAT                  bGPIO(oGPIO_G, oGPIO_DAT)
00156 #define GPGUP                   bGPIO(oGPIO_G, oGPIO_UP)
00157 #define GPHCON                  bGPIO(oGPIO_H, oGPIO_CON)
00158 #define GPHDAT                  bGPIO(oGPIO_H, oGPIO_DAT)
00159 #define GPHUP                   bGPIO(oGPIO_H, oGPIO_UP)
00160 #define MISCCR                  bGPIO(oMISCCR, 0)
00161 #define DCLKCON                 bGPIO(oDCLKCON, 0)
00162 #define EXTINT0                 bGPIO(oEXTINT0, 0)
00163 #define EXTINT1                 bGPIO(oEXTINT1, 0)
00164 #define EXTINT2                 bGPIO(oEXTINT2, 0)
00165 #define EINTFLT0                bGPIO(oEINTFLT0, 0)
00166 #define EINTFLT1                bGPIO(oEINTFLT1, 0)
00167 #define EINTFLT2                bGPIO(oEINTFLT2, 0)
00168 #define EINTFLT3                bGPIO(oEINTFLT3, 0)
00169 #define EINTMASK                bGPIO(oEINTMASK, 0)
00170 #define EINTPEND                bGPIO(oEINTPEND, 0)
00171 
00172 /* UART */
00173 #define UART_CTL_BASE           0x50000000
00174 #define UART0_CTL_BASE          UART_CTL_BASE
00175 #define UART1_CTL_BASE          UART_CTL_BASE + 0x4000
00176 #define UART2_CTL_BASE          UART_CTL_BASE + 0x8000
00177 #define bUART(x, Nb)            __REGl(UART_CTL_BASE + (x)*0x4000 + (Nb))
00178 #define bUARTb(x, Nb)           __REGb(UART_CTL_BASE + (x)*0x4000 + (Nb))
00179 /* Offset */
00180 #define oULCON                  0x00    /* R/W, UART line control register */
00181 #define oUCON                   0x04    /* R/W, UART control register */
00182 #define oUFCON                  0x08    /* R/W, UART FIFO control register */
00183 #define oUMCON                  0x0C    /* R/W, UART modem control register */
00184 #define oUTRSTAT                0x10    /* R  , UART Tx/Rx status register */
00185 #define oUERSTAT                0x14    /* R  , UART Rx error status register */
00186 #define oUFSTAT                 0x18    /* R  , UART FIFO status register */
00187 #define oUMSTAT                 0x1C    /* R  , UART Modem status register */
00188 #define oUTXHL                  0x20    /*   W, UART transmit(little-end) buffer */
00189 #define oUTXHB                  0x23    /*   W, UART transmit(big-end) buffer */
00190 #define oURXHL                  0x24    /* R  , UART receive(little-end) buffer */
00191 #define oURXHB                  0x27    /* R  , UART receive(big-end) buffer */
00192 #define oUBRDIV                 0x28    /* R/W, Baud rate divisor register */
00193 /* Registers */
00194 #define ULCON0                  bUART(0, oULCON)
00195 #define UCON0                   bUART(0, oUCON)
00196 #define UFCON0                  bUART(0, oUFCON)
00197 #define UMCON0                  bUART(0, oUMCON)
00198 #define UTRSTAT0                bUART(0, oUTRSTAT)
00199 #define UERSTAT0                bUART(0, oUERSTAT)
00200 #define UFSTAT0                 bUART(0, oUFSTAT)
00201 #define UMSTAT0                 bUART(0, oUMSTAT)
00202 #define UTXH0                   bUARTb(0, oUTXHL)
00203 #define URXH0                   bUARTb(0, oURXHL)
00204 #define UBRDIV0                 bUART(0, oUBRDIV)
00205 #define ULCON1                  bUART(1, oULCON)
00206 #define UCON1                   bUART(1, oUCON)
00207 #define UFCON1                  bUART(1, oUFCON)
00208 #define UMCON1                  bUART(1, oUMCON)
00209 #define UTRSTAT1                bUART(1, oUTRSTAT)
00210 #define UERSTAT1                bUART(1, oUERSTAT)
00211 #define UFSTAT1                 bUART(1, oUFSTAT)
00212 #define UMSTAT1                 bUART(1, oUMSTAT)
00213 #define UTXH1                   bUARTb(1, oUTXHL)
00214 #define URXH1                   bUARTb(1, oURXHL)
00215 #define UBRDIV1                 bUART(1, oUBRDIV)
00216 #define ULCON2                  bUART(2, oULCON)
00217 #define UCON2                   bUART(2, oUCON)
00218 #define UFCON2                  bUART(2, oUFCON)
00219 #define UMCON2                  bUART(2, oUMCON)
00220 #define UTRSTAT2                bUART(2, oUTRSTAT)
00221 #define UERSTAT2                bUART(2, oUERSTAT)
00222 #define UFSTAT2                 bUART(2, oUFSTAT)
00223 #define UMSTAT2                 bUART(2, oUMSTAT)
00224 #define UTXH2                   bUARTb(2, oUTXHL)
00225 #define URXH2                   bUARTb(2, oURXHL)
00226 #define UBRDIV2                 bUART(2, oUBRDIV)
00227 /* ... */
00228 #define UTRSTAT_TX_EMPTY        (1 << 2)
00229 #define UTRSTAT_RX_READY        (1 << 0)
00230 #define UART_ERR_MASK           0xF 
00231 
00232 /* Interrupts */
00233 #define INT_CTL_BASE            0x4A000000
00234 #define bINT_CTL(Nb)            __REG(INT_CTL_BASE + (Nb))
00235 /* Offset */
00236 #define oSRCPND                 0x00
00237 #define oINTMOD                 0x04
00238 #define oINTMSK                 0x08
00239 #define oPRIORITY               0x0a
00240 #define oINTPND                 0x10
00241 #define oINTOFFSET              0x14
00242 #define oSUBSRCPND              0x18
00243 #define oINTSUBMSK              0x1C
00244 /* Registers */
00245 #define SRCPND                  bINT_CTL(oSRCPND)
00246 #define INTMOD                  bINT_CTL(oINTMOD)
00247 #define INTMSK                  bINT_CTL(oINTMSK)
00248 #define PRIORITY                bINT_CTL(oPRIORITY)
00249 #define INTPND                  bINT_CTL(oINTPND)
00250 #define INTOFFSET               bINT_CTL(oINTOFFSET)
00251 #define SUBSRCPND               bINT_CTL(oSUBSRCPND)
00252 #define INTSUBMSK               bINT_CTL(oINTSUBMSK)
00253 
00254 #define INT_ADCTC               (1 << 31)       /* ADC EOC interrupt */
00255 #define INT_RTC                 (1 << 30)       /* RTC alarm interrupt */
00256 #define INT_SPI1                (1 << 29)       /* UART1 transmit interrupt */
00257 #define INT_UART0               (1 << 28)       /* UART0 transmit interrupt */
00258 #define INT_IIC                 (1 << 27)       /* IIC interrupt */
00259 #define INT_USBH                (1 << 26)       /* USB host interrupt */
00260 #define INT_USBD                (1 << 25)       /* USB device interrupt */
00261 #define INT_RESERVED24          (1 << 24)
00262 #define INT_UART1               (1 << 23)       /* UART1 receive interrupt */
00263 #define INT_SPI0                (1 << 22)       /* SPI interrupt */
00264 #define INT_MMC                 (1 << 21)       /* MMC interrupt */
00265 #define INT_DMA3                (1 << 20)       /* DMA channel 3 interrupt */
00266 #define INT_DMA2                (1 << 19)       /* DMA channel 2 interrupt */
00267 #define INT_DMA1                (1 << 18)       /* DMA channel 1 interrupt */
00268 #define INT_DMA0                (1 << 17)       /* DMA channel 0 interrupt */
00269 #define INT_LCD                 (1 << 16)       /* reserved for future use */
00270 #define INT_UART2               (1 << 15)       /* UART 2 interrupt  */
00271 #define INT_TIMER4              (1 << 14)       /* Timer 4 interrupt */
00272 #define INT_TIMER3              (1 << 13)       /* Timer 3 interrupt */
00273 #define INT_TIMER2              (1 << 12)       /* Timer 2 interrupt */
00274 #define INT_TIMER1              (1 << 11)       /* Timer 1 interrupt */
00275 #define INT_TIMER0              (1 << 10)       /* Timer 0 interrupt */
00276 #define INT_WDT                 (1 << 9)        /* Watch-Dog timer interrupt */
00277 #define INT_TICK                (1 << 8)        /* RTC time tick interrupt  */
00278 #define INT_BAT_FLT             (1 << 7)
00279 #define INT_RESERVED6           (1 << 6)        /* Reserved for future use */
00280 #define INT_EINT8_23            (1 << 5)        /* External interrupt 8 ~ 23 */
00281 #define INT_EINT4_7             (1 << 4)        /* External interrupt 4 ~ 7 */
00282 #define INT_EINT3               (1 << 3)        /* External interrupt 3 */
00283 #define INT_EINT2               (1 << 2)        /* External interrupt 2 */
00284 #define INT_EINT1               (1 << 1)        /* External interrupt 1 */
00285 #define INT_EINT0               (1 << 0)        /* External interrupt 0 */
00286 
00287 #define INT_ADC                 (1 << 10)
00288 #define INT_TC                  (1 << 9)
00289 #define INT_ERR2                (1 << 8)
00290 #define INT_TXD2                (1 << 7)
00291 #define INT_RXD2                (1 << 6)
00292 #define INT_ERR1                (1 << 5)
00293 #define INT_TXD1                (1 << 4)
00294 #define INT_RXD1                (1 << 3)
00295 #define INT_ERR0                (1 << 2)
00296 #define INT_TXD0                (1 << 1)
00297 #define INT_RXD0                (1 << 0)
00298 
00299 /* NAND Flash Controller */
00300 #define NAND_CTL_BASE           0x4E000000
00301 #define bINT_CTL(Nb)            __REG(INT_CTL_BASE + (Nb))
00302 /* Offset */
00303 #define oNFCONF                 0x00
00304 #define oNFCONT                 0x04
00305 #define oNFCMD                  0x08
00306 #define oNFADDR                 0x0c
00307 #define oNFDATA                 0x10
00308 #define oNFSTAT                 0x20
00309 #define oNFECC                  0x2c
00310 
00311 
00312 /* PWM Timer */
00313 #define bPWM_TIMER(Nb)          __REG(0x51000000 + (Nb))
00314 #define bPWM_BUFn(Nb,x)         bPWM_TIMER(0x0c + (Nb)*0x0c + (x))
00315 /* Registers */
00316 #define TCFG0                   bPWM_TIMER(0x00)
00317 #define TCFG1                   bPWM_TIMER(0x04)
00318 #define TCON                    bPWM_TIMER(0x08)
00319 #define TCNTB0                  bPWM_BUFn(0,0x0)
00320 #define TCMPB0                  bPWM_BUFn(0,0x4)
00321 #define TCNTO0                  bPWM_BUFn(0,0x8)
00322 #define TCNTB1                  bPWM_BUFn(1,0x0)
00323 #define TCMPB1                  bPWM_BUFn(1,0x4)
00324 #define TCNTO1                  bPWM_BUFn(1,0x8)
00325 #define TCNTB2                  bPWM_BUFn(2,0x0)
00326 #define TCMPB2                  bPWM_BUFn(2,0x4)
00327 #define TCNTO2                  bPWM_BUFn(2,0x8)
00328 #define TCNTB3                  bPWM_BUFn(3,0x0)
00329 #define TCMPB3                  bPWM_BUFn(3,0x4)
00330 #define TCNTO3                  bPWM_BUFn(3,0x8)
00331 #define TCNTB4                  bPWM_BUFn(4,0x0)
00332 #define TCNTO4                  bPWM_BUFn(4,0x4)
00333 /* Fields */
00334 #define fTCFG0_DZONE            Fld(8,16)       /* the dead zone length (= timer 0) */
00335 #define fTCFG0_PRE1             Fld(8,8)        /* prescaler value for time 2,3,4 */
00336 #define fTCFG0_PRE0             Fld(8,0)        /* prescaler value for time 0,1 */
00337 #define fTCFG1_MUX4             Fld(4,16)
00338 /* bits */
00339 #define TCFG0_DZONE(x)          FInsrt((x), fTCFG0_DZONE)
00340 #define TCFG0_PRE1(x)           FInsrt((x), fTCFG0_PRE1)
00341 #define TCFG0_PRE0(x)           FInsrt((x), fTCFG0_PRE0)
00342 #define TCON_4_AUTO             (1 << 22)       /* auto reload on/off for Timer 4 */
00343 #define TCON_4_UPDATE           (1 << 21)       /* manual Update TCNTB4 */
00344 #define TCON_4_ONOFF            (1 << 20)       /* 0: Stop, 1: start Timer 4 */
00345 #define COUNT_4_ON              (TCON_4_ONOFF*1)
00346 #define COUNT_4_OFF             (TCON_4_ONOFF*0)
00347 #define TCON_3_AUTO     (1 << 19)       /* auto reload on/off for Timer 3 */
00348 #define TIMER3_ATLOAD_ON        (TCON_3_AUTO*1)
00349 #define TIMER3_ATLAOD_OFF       FClrBit(TCON, TCON_3_AUTO)
00350 #define TCON_3_INVERT   (1 << 18)       /* 1: Inverter on for TOUT3 */
00351 #define TIMER3_IVT_ON   (TCON_3_INVERT*1)
00352 #define TIMER3_IVT_OFF  (FClrBit(TCON, TCON_3_INVERT))
00353 #define TCON_3_MAN      (1 << 17)       /* manual Update TCNTB3,TCMPB3 */
00354 #define TIMER3_MANUP    (TCON_3_MAN*1)
00355 #define TIMER3_NOP      (FClrBit(TCON, TCON_3_MAN))
00356 #define TCON_3_ONOFF    (1 << 16)       /* 0: Stop, 1: start Timer 3 */
00357 #define TIMER3_ON       (TCON_3_ONOFF*1)
00358 #define TIMER3_OFF      (FClrBit(TCON, TCON_3_ONOFF))
00359 /* macros */
00360 #define GET_PRESCALE_TIMER4(x)  FExtr((x), fTCFG0_PRE1)
00361 #define GET_DIVIDER_TIMER4(x)   FExtr((x), fTCFG1_MUX4)
00362 
00363 /*
00364  * NAND Flash Controller (Page 6-1 ~ 6-8)
00365  *
00366  * Register
00367    NFCONF   NAND Flash Configuration    [word, R/W, 0x00000000]
00368    NFCMD    NAND Flash Command Set      [word, R/W, 0x00000000]
00369    NFADDR   NAND Flash Address Set      [word, R/W, 0x00000000]
00370    NFDATA   NAND Flash Data             [word, R/W, 0x00000000]
00371    NFSTAT   NAND Flash Status           [word, R, 0x00000000]
00372    NFECC    NAND Flash ECC              [3 bytes, R, 0x00000000]
00373  *
00374  */
00375 #define bNAND_CTL(Nb)   __REG(0x4e000000 + (Nb))
00376 #define NFCONF          bNAND_CTL(0x00)
00377 #define NFCONT          bNAND_CTL(0x04)
00378 #define NFCMD       bNAND_CTL(0x08)
00379 #define NFADDR      bNAND_CTL(0x0c)
00380 #define NFDATA      __REGb(0x4e000000 + (0x10))
00381 #define NFSTAT      bNAND_CTL(0x20)
00382 #define NFECC       bNAND_CTL(0x2c)
00383 
00384 #define fNFCONF_TWRPH1   Fld(3,4)
00385 #define NFCONF_TWRPH1    FMsk(fNFCONF_TWRPH1)
00386 #define NFCONF_TWRPH1_7  FInsrt(0x7, fNFCONF_TWRPH1) /* 7 */
00387 #define fNFCONF_TWRPH0   Fld(3,8)
00388 #define NFCONF_TWRPH0    FMsk(fNFCONF_TWRPH0)
00389 #define NFCONF_TWRPH0_7  FInsrt(0x7, fNFCONF_TWRPH0) /* 7 */
00390 #define fNFCONF_TACLS    Fld(3,12)
00391 #define NFCONF_TACLS     FMsk(fNFCONF_TACLS)
00392 #define NFCONF_TACLS_7   FInsrt(0x7, fNFCONF_TACLS) /* 7 */
00393 #define fNFCONT_nFCE     Fld(1,1)
00394 #define NFCONT_nFCE      FMsk(fNFCONT_nFCE)
00395 #define NFCONT_nFCE_LOW  FInsrt(0x0, fNFCONT_nFCE) /* active */
00396 #define NFCONT_nFCE_HIGH FInsrt(0x1, fNFCONT_nFCE) /* inactive */
00397 
00398 #define fNFCONT_ECC      Fld(1,4)
00399 #define NFCONT_ECC       FMsk(fNFCONT_ECC)
00400 #define NFCONT_ECC_NINIT FInsrt(0x0, fNFCONT_ECC) /* not initialize */
00401 #define NFCONT_ECC_INIT  FInsrt(0x1, fNFCONT_ECC)    /* initialize */
00402 
00403 #define fNFCONT_MAINECC  Fld(1,5)
00404 #define NFCONT_MAINECC       FMsk(fNFCONT_MAINECC)
00405 #define NFCONT_MAINECC_UNLOCK FInsrt(0x0, fNFCONT_MAINECC) 
00406 #define NFCONT_MAINECC_LOCK   FInsrt(0x1, fNFCONT_MAINECC)
00407 
00408 #define fNFCONF_ADDRSTEP Fld(1,13)                 /* Addressing Step */
00409 #define NFCONF_ADDRSTEP  FMsk(fNFCONF_ADDRSTEP)
00410 
00411 /* S3C2440 H/W Set */
00412 #define fNFCONF_PAGESIZE Fld(1,2)
00413 #define NFCONF_PAGESIZE  FMsk(fNFCONF_PAGESIZE)
00414 #define NFCONF_PAGESIZE_256  FInsrt(0x0, fNFCONF_PAGESIZE) /* 256 bytes */
00415 #define NFCONF_PAGESIZE_512  FInsrt(0x1, fNFCONF_PAGESIZE) /* 512 bytes */
00416 
00417 #define fNFCONT_FCTRL    Fld(1,0)  /* Flash controller enable/disable */
00418 #define NFCONT_FCTRL     FMsk(fNFCONT_FCTRL)
00419 #define NFCONT_FCTRL_DIS FInsrt(0x0, fNFCONT_FCTRL) /* Disable */
00420 #define NFCONT_FCTRL_EN  FInsrt(0x1, fNFCONT_FCTRL) /* Enable */
00421 
00422 #define NFSTAT_RnB      (1 << 2)
00423 
00424 
00425 /*
00426  * Power Management
00427  */
00428 #define SPI_CLK         (1 << 18)
00429 #define IIS_CLK         (1 << 17)
00430 #define IIC_CLK         (1 << 16
00431 #define ADC_CLK         (1 << 15)
00432 #define RTC_CLK         (1 << 14)
00433 #define GPIO_CLK        (1 << 13)
00434 #define UART2_CLK       (1 << 12)
00435 #define UART1_CLK       (1 << 11)
00436 #define UART0_CLK       (1 << 10)
00437 #define SDI_CLK         (1 << 9)
00438 #define PWM_CLK         (1 << 8)
00439 #define USBSLAVE_CLK    (1 << 7)
00440 #define USBHOST_CLK     (1 << 6)
00441 #define LCDC_CLK        (1 << 5)
00442 #define NANDCTL_CLK     (1 << 4)
00443 #define SLEEP_ON        (1 << 3)
00444 #define IDLE            (1 << 2)
00445 
00446 #define GSTATUS(Nb)     __REG(0x560000AC + (Nb*4))
00447 #define GSTATUS0        GSTATUS(0)
00448 #define GSTATUS1        GSTATUS(1)
00449 #define GSTATUS2        GSTATUS(2)
00450 #define GSTATUS3        GSTATUS(3)
00451 #define GSTATUS4        GSTATUS(4)
00452 #define PMST            GSTATUS2
00453 #define PMSR0           GSTATUS3
00454 #define PMSR1           GSTATUS4
00455 #define PMCTL0          CLKCON
00456 #define PMCTL1          MISCCR
00457 #define SCLKE           (1 << 19)
00458 #define SCLK1           (1 << 18)
00459 #define SCLK0           (1 << 17)
00460 #define USBSPD1         (1 << 13)
00461 #define USBSPD0         (1 << 12)
00462 #define PMST_HWR        (1 << 0)
00463 #define PMST_SMR        (1 << 1)
00464 #define PMST_WDR        (1 << 2)
00465 
00466 
00467 #define HIDDEN(Nb)      __REG(0x560000C0 + (Nb*4))
00468 #define FLTOUT          HIDDEN(0)
00469 #define DSC0            HIDDEN(1)
00470 #define DSC1            HIDDEN(2)
00471 #define MSLCON          HIDDEN(3)
00472 
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